TPS75715 datasheet(13/25 Pages) TI

13 / 25 page

TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

THERMAL INFORMATION

The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it

dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax)

above which normal operation is not assured. A system designer must design the operating environment so

that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The

two main environmental variables that a designer can use to improve thermal performance are air flow and

external heatsinks. The purpose of this information is to aid the designer in determining the proper operating

environment for a linear regulator that is operating at a specific power level.

In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as:

max

+ V

I(avg) *

O(avg)

O(avg) )

I(avg)

(Q)

(1)

Where:

VI(avg) is the average input voltage.

VO(avg) is the average output voltage.

IO(avg) is the average output current.

I(Q) is the quiescent current.

For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;

therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding

the ambient temperature (TA) and the increase in temperature due to the regulator’s power dissipation. The

temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal

resistances between the junction and the case (RθJC), the case to heatsink (RθCS), and the heatsink to ambient

(RθSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the

device, the more surface area available for power dissipation and the lower the object’s thermal resistance.

Figure 21 illustrates these thermal resistances for (a) a TO–220 package attached to a heatsink, and (b) a

TO–263 package mounted on a JEDEC High-K board.

θJC

θCS

θSA

(a)

(b)

TO–263 Package

TO–220 Package

Figure 21. Thermal Resistances

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