TSB42AB4PDT datasheet(21/183 Pages) TI

21 / 183 page

2−10

2.5.1.3

High-Speed Data Interface (continued)

NAME

PDT PIN NO.

PGE PIN NO.

I/O

DESCRIPTION

HSDIA_ENZ

HSDIA port access enable. Used to indicate valid data

for 1394 transmit (host write) or 1394 receive (host read)

operations. Asserting HSDIA_ENZ during host writes

latches the data on the next HSDIA_CLK rising edge.

Asserting HSDIA_ENZ during host reads, presents

received 1394 data from internal buffers on the next

HSDIA_CLK rising edge.

HSDIA_ENZ polarity is programmable and defaults to

active high.

HSDIB_ENZ

121

135

HSDIB port access enable. Used to indicate valid data

for 1394 transmit (host write) operations or 1394 receive

(host read) operations. Asserting HSDIB_ENZ during

host writes latches the data on the next HSDIB_CLK

rising edge. Asserting HSDIB_ENZ during host reads

presents received 1394 data from internal buffers on the

next HSDIB_CLK rising edge.

HSDIB_ENZ polarity is programmable and defaults to

active high.

2.5.1.4

Microcontroller Interface (MCIF)†

NAME

PDT PIN NO.

PGE PIN NO.

I/O

DESCRIPTION

INT

Interrupt. This is the ceLynx interrupt output to the host.

This signal is active-low. When this pin is not used, add a

weak pull-up (1 k

Ω to 10 kΩ).

MCIF_A[9:1]

65, 66, 67, 68,

70, 71, 72, 73,

75, 76, 77, 78,

80, 81, 82, 83,

Microcontroller interface address bus. MCIF_A9 is the

MSB and MCIF_A1 is the LSB. Users should connect their

LSB+1 address pin to MCIF_A1 (byte access is not

allowed).

MCIF_ACKZ

Acknowledge signal. Indicates to the host controller the

completion of the current read or write access.

When MCIF_ACKZ asserts (low) during host writes, data

has been successfully written to the specified address.

When MCIF_ACKZ asserts (low) during host reads, this

indicates that data is valid and may be read by the host.

The MCIF_ACKZ polarity is programmable and defaults to

active low. When this pin is not used, add a weak pull-up (1

Ω to 10 kΩ).

MCIF_CSZ

ceLynx chip select. Enables the ceLynx to perform read or

write transactions on the microcontroller interface. The

MCIF_CSZ polarity is programmable and defaults to active

low.

MCIF_D[15:0]

44, 45, 46, 49,

50, 51, 52, 53,

55, 56, 57, 58,

60, 61, 62, 63

50, 51, 52, 55,

56, 57, 58, 59,

61, 62, 63, 64,

66, 67, 68, 69

I/O

Microcontroller

interface

bidirectional

data

bus.

MCIF_D15 is the MSB on this bus, and MCIF_D0 is the

LSB.

MCIF_RWZ

Read/write indicator. Indicates whether the current

pending access is a read or a write.

MCIF_RWZ polarity is programmable and defaults to

active high during read operations and active low during

write operations.

TSB42AB4PDT Datasheet(PDF) 21 Page - Texas Instruments

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