ADE7758ARWRL datasheet(55/68 Pages) AD

55 / 68 page

ADE7758

Rev. A | Page 55 of 68

INTERRUPT TIMING

The ADE7758 Serial Interface section should be reviewed first

before reviewing this interrupt timing section. As previously

described, when the IRQ output goes low, the MCU ISR must

read the interrupt status register in order to determine the

source of the interrupt. When reading the interrupt status

edge of SCLK of the first byte transfer (read interrupt status

bit of the next 8-bit transfer is shifted out (interrupt status

this time, the IRQ output goes low again. If no interrupt is

pending, the IRQ output remains high.

ADE7758 SERIAL INTERFACE

The ADE7758 has a built-in SPI interface. The serial interface

of the ADE7758 is made of four signals: SCLK, DIN, DOUT,

and CS. The serial clock for a data transfer is applied at the

SCLK logic input. This logic input has a Schmitt trigger input

structure that allows slow rising (and falling) clock edges to be

used. All data transfer operations are synchronized to the serial

clock. Data is shifted into the ADE7758 at the DIN logic input

on the falling edge of SCLK. Data is shifted out of the ADE7758

at the DOUT logic output on a rising edge of SCLK. The CS

logic input is the chip select input. This input is used when

multiple devices share the serial bus. A falling edge on CS also

resets the serial interface and places the ADE7758 in commu-

nications mode. The CS input should be driven low for the

entire data transfer operation. Bringing CS high during a data

transfer operation aborts the transfer and place the serial bus in

a high impedance state. The CS logic input may be tied low if

the ADE7758 is the only device on the serial bus. However, with

CS tied low, all initiated data transfer operations must be fully

completed. The LSB of each register must be transferred

because there is no other way of bringing the ADE7758 back

into communications mode without resetting the entire device,

i.e., performing a software reset using Bit 6 of the OPMODE[7:0]

accessible via several on-chip registers (see Figure 86). The

contents of these registers can be updated or read using the on-

chip serial interface. After a falling edge on CS, the ADE7758 is

placed in communications mode. In communications mode, the

ADE7758 expects the first communication to be a write to the

internal communications register. The data written to the

communications register contains the address and specifies the

next data transfer to be a read or a write command. Therefore,

all data transfer operations with the ADE7758, whether a read

or a write, must begin with a write to the communications

COMMUNICATIONS

OUT

ADDRESS

DECODE

DIN

DOUT

Figure 86. Addressing ADE7758 Registers via the Communications Register

GLOBAL

INTERRUPT

MASK

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

CLEAR MCU

INTERRUPT

FLAG

READ

STATUS WITH

RESET (0x1A)

ISR ACTION

(BASED ON STATUS CONTENTS)

MCU

INTERRUPT

FLAG SET

PROGRAM

SEQUENCE

JUMP

ISR

JUMP

ISR

IRQ

Figure 87. ADE7758 Interrupt Management

STATUS REGISTER CONTENTS

SCLK

DIN

DOUT

READ STATUS REGISTER COMMAND

000

DB15

DB8

DB7

DB0

t11

t12

IRQ

Figure 88. ADE7758 Interrupt Timing

ADE7758ARWRL Datasheet(PDF) 55 Page - Analog Devices

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