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DAC7573IPW Datasheet(PDF) 5 Page - Texas Instruments

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Part # DAC7573IPW
Description  QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER
PDF  30 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC7573IPW Datasheet(HTML) 5 Page - Texas Instruments

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DAC7573
SLAS398 – SEPTEMBER 2003
TIMING CHARACTERISTICS (continued)
V
DD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Standard mode
20
× 0.1C
B
1000
ns
Rise time of SCL signal after
Fast mode
20
× 0.1C
B
300
ns
a repeated START condition
tRCL1
and after an acknowledge
High-speed mode, CB = 100 pF max
10
80
ns
BIT
High-speed mode, CB = 400 pF max
20
160
ns
Standard mode
20
× 0.1C
B
300
ns
Fast mode
20
× 0.1C
B
300
ns
tFCL
Fall time of SCL signal
High-speed mode, CB = 100 pF max
10
40
ns
High-speed mode, CB = 400 pF max
20
80
ns
Standard mode
20
× 0.1C
B
1000
ns
Fast mode
20
× 0.1C
B
300
ns
tRDA
Rise time of SDA signal
High-speed mode, CB = 100 pF max
10
80
ns
High-speed mode, CB = 400 pF max
20
160
ns
Standard mode
20
× 0.1C
B
300
ns
Fast mode
20
× 0.1C
B
300
ns
tFDA
Fall time of SDA signal
High-speed mode, CB = 100 pF max
10
80
ns
High-speed mode, CB = 400 pF max
20
160
ns
Standard mode
4.0
µs
Setup time for STOP con-
tSU; tSTO
Fast mode
600
ns
dition
High-speed mode
160
ns
Capacitive load for SDA and
CB
400
pF
SCL
Fast mode
50
ns
Pulse width of spike sup-
tSP
pressed
High-speed mode
10
ns
Standard mode
Noise margin at the HIGH
VNH
level for each connected de-
Fast mode
0.2 VDD
V
vice (including hysteresis)
High-speed mode
Standard mode
Noise margin at the LOW
VNL
level for each connected de-
Fast mode
0.1 VDD
V
vice (including hysteresis)
High-speed mode
5



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