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DM9081 Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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DM9081 Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
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10 / 22 page  DM9081 10 Final Version: DM9081-DS-F01 April 22, 1997 Normal Mode In normal mode, TESTPIN0 and TESTPIN1 must be pulled high. The COL_LED, AUI1_CRS_LED and AUI2_CRS_LED pins are defined as minimum mode, whereas the other LED drive pins require external devices to display the status from the LED pins. These pins transmit information from the DM9081 by first sending Bit 7. A detailed timing diagram is given in Figure 3. The shift logic and latch device shown in Figure 4 is used to convert received serial data into byte- oriented data. The output data is used to drive the LED. LED Latch The LED_LATCH pin is used to latch the byte-oriented data. The rising edge of the TCK clock, occurring on the high state LED_LATCH, is used to strobe in the state of the following LED pins. B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B1 B6 B5 B4 B3 B2 B7 TCK LI_RXn LED_LATCH Figure 3. Serial LED Signal Timing Figure 4. Normal Mode Implementation |
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