DS1086 Spread-Spectrum EconOscillator

10

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ADDR Register

The A0, A1, A2 bits determine the 2-wire slave address.

The WC bit determines if the EEPROM is to be written

to after register contents have been changed. If

WC = 0 (default), EEPROM is written automatically after

a WRITE EE command. If WC = 1, the EEPROM is only

written when the WRITE EE command is issued. In

applications where the register contents are frequently

written, the WC bit should be set to 1. Otherwise, it is

necessary to wait for an EEPROM write cycle to com-

plete between writing to the registers. This also pre-

vents wearing out the EEPROM. Regardless of the

value of the WC bit, the value of the ADDR register is

always written immediately to EEPROM. When the

WRITE EE command has been received, the contents

of the registers are written into the EEPROM, thus lock-

ing in the register settings.

RANGE Register

This read-only register contains a copy of the factory-

set offset (OS). This value can be read to determine the

default value of the OFFSET register when program-

ming a new master oscillator frequency.

WRITE EE Command

This command is used to write data from RAM to

EEPROM when the WC bit in ADDR register is 1. See

the ADDR Register section for more details.

Example Frequency Calculations

Example #1: Calculate the register values needed to

generate a desired output frequency of 11.0592MHz.

Since the desired frequency is not within the valid mas-

ter oscillator range of 66MHz to 133MHz, the prescaler

equals 0 to 8 (and x is the value that is programmed

into the P3 to P0 bits of the PRESCALER register).

Equation 1 shows the relationship between the desired

frequency, the master oscillator frequency, and the

prescaler.

By trial and error, x is incremented from 0 to 8 in

Equation 2, finding values of x that yield master oscilla-

tor frequencies within the range of 66MHz to 133MHz.

Equation 2 shows that a prescaler of 8 (x = 3) and a

master oscillator frequency of 88.4736MHz generates

our desired frequency. In terms of the device register, x

= 3 is programmed in the lower four bits of the

PRESCALER register. Writing 03h to the PRESCALER

register sets the PRESCALER to 8 (and 4% peak

dither). Be aware that the J0 bit also resides in the

PRESCALER register.

Once the target master oscillator frequency has been

calculated, the value of offset can be determined.

OS - 2. However, choosing OS - 1 would be a poor

choice since 88.4736MHz is so close to OS - 1’s mini-

mum frequency. On the other hand, OS - 2 is ideal

since 88.4736MHz is very close to the center of

OS - 2’s frequency span. Before the OFFSET register

can be programmed, the default value of offset (OS)

f

f

prescaler

f

DESIRED

MASTER OSCILLATOR

MASTER OSCILLATOR

X

=

=

2

(2)

(3)

STOP

CONDITION

OR REPEATED

START

CONDITION

REPEATED IF MORE BYTES

ARE TRANSFERRED

ACK

START

CONDITION

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

MSB

SCL

SDA

R/W

DIRECTION

BIT

12

6

7

8

9

12

8

9

3–7

Figure 4. 2-Wire Data Transfer Protocol