DS1646P datasheet(5/11 Pages) DALLAS

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DS1646/DS1646P

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WRITING DATA TO RAM OR CLOCK

The DS1646 is in the write mode whenever WE and CE are in their active state. The start of a write is

referenced to the latter occurring high to low transition of WE and CE . The addresses must be held valid

throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of

another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH

afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be

active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE

transitioning low the data bus can become active with read data defined by the address inputs. A low

transition on WE will then disable the outputs tWEZ after WE goes active.

DATA RETENTION MODE

When VCC is within nominal limits (VCC > 4.5 volts) the DS1646 can be accessed as described above with

read or write cycles. However, when VCC is below the power-fail point VPF (point at which write

protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished

internally by inhibiting access via the CE signal. At this time the power-fail output signal ( PFO ) will be

driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the

level of the internal battery supply, power input is switched from the VCC pin to the internal battery and

clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal

level.

DS1646P Datasheet(PDF) 5 Page - Dallas Semiconductor