DS1501/DS1511 Y2K Watchdog Real-Time Clock

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Control B Register (0Fh)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TE

CS

BME

TPE

TIE

KIE

WDE

WDS

TE, Transfer Enable Bit (0Fh Bit 7)

When the TE bit is 1, the update transfer functions normally by advancing the counts once per second. When the

TE bit is written to 0, any update transfer is inhibited and the program can initialize the time and calendar bytes

without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. TE is a

read/write bit that is not modified by internal functions of the DS1501/DS1511.

CS, Crystal Select Bit (0Fh Bit 6)

When CS is set to 0, the oscillator is configured for operation with a crystal that has a 6pF specified load

capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is disabled in the DS1511 module

and should be set to CS = 0.

BME, Burst-Mode Enable Bit (0Fh Bit 5)

The burst-mode enable bit allows the extended user RAM address registers to automatically increment for

consecutive reads and writes. When BME is set to 1, the automatic incrementing is enabled; when BME is set to 0,

the automatic incrementing is disabled.

TPE, Time-of-Day/Date Alarm Power-Enable Bit (0Fh Bit 4)

The wakeup feature is controlled through the TPE bit. When the TDF flag bit is set to 1, if TPE is 1, the

PWR pin is

driven active. Therefore, setting TPE to 1 enables the wakeup feature. Writing a 0 to TPE disables the wakeup

feature.

TIE, Time-of-Day/Date Alarm Interrupt-Enable Bit (0Fh Bit 3)

The TIE bit allows the TDF flag to assert an interrupt. When the TDF flag bit is set to 1, if TIE is 1, the IRQF flag bit

is set to 1. Writing a 0 to the TIE bit prevents the TDF flag from setting the IRQF flag. This bit is automatically

KIE, Kickstart Enable-Interrupt Bit (0Fh Bit 2)

The KIE bit allows the KSF flag to assert an interrupt. When the KSF flag bit is set to 1, if KIE is a 1, the IRQF flag

bit is set to 1. Writing a 0 to the KIE bit prevents the KSF flag from setting the IRQF flag. This bit is automatically

WDE, Watchdog Enable Bit (0Fh Bit 1)

When WDE is set to 1, the watchdog function is enabled, and either the

IRQ or RST pin is pulled active, based on

the state of the WDS and WDF bits. This bit is automatically cleared to logic 0 to by the internal power-on reset

WDS, Watchdog Steering Bit (0Fh Bit 0)

If WDS is 0 when the watchdog flag bit WDF is set to 1, the

IRQ pin is pulled low. If WDS is 1 when WDF is set to

1, the watchdog outputs a negative pulse on the

RST output. The WDE bit resets to 0 immediately after RST goes

rises above the power-fail voltage.

CLOCK OSCILLATOR CONTROL

The clock oscillator can be stopped at any time. To increase the shelf life of a backup lithium-battery source, the

oscillator can be turned off to minimize current drain from the battery. The

EOSC bit is used to control the state of

the oscillator, and must be set to 0 for the oscillator to function.

USING THE WATCHDOG TIMER

The watchdog timer can be used to restart an out-of-control processor. The watchdog timer is user programmable

in 10ms intervals ranging from 0.01 seconds to 99.99 seconds. The user programs the watchdog timer by writing

the timeout value into the two BCD watchdog registers (0Ch and 0Dh). The watchdog reloads and restarts

whenever the watchdog times out. If either watchdog register is nonzero, a timeout sets the WDF bit to 1,