®

INA120

6

T

Time (10

µs/ Division)

LARGE-SIGNAL TRANSIENT

RESPONSE G = 100

SMALL-SIGNAL TRANSIENT RESPONSE

G = 100

Time (5

µs/ Division)

APPLICATION INFORMATION

Figure 1 shows the basic connections required for operation

of the INA120. Applications with noisy or high impedance

power supply lines may require decoupling capacitors close

to the device pins as shown. The differential input voltage

is applied to pins 16 and 3.

The output is referred to the output common reference

terminal, pin 18. This terminal must have a low-impedance

connection to ground. A resistance of 1

Ω or greater in series

with the common terminal could degrade common-mode

rejection beyond the specified value.

SETTING THE GAIN

Gains of 1, 10, 100 or 1000 can be configured by intercon-

necting the gain-set pins as shown in the table of Figure 1.

These pin-strapped gains provide best gain accuracy and

drift because they are determined by the ratios of accurately

trimmed and matched on-chip resistors.

Digital gain control can be achieved using an analog multi-

plexer as shown in Figure 2. Since the switches are in series

with the high impedance gain-sense connections, pins 4 and

15, their series resistance does not significantly affect gain

error or drift. Gain error at G = 1 is slightly higher than with

direct pin connections shown in Figure 1. The gain is

selected with a two-bit address, A

Enable control is directly connected to V+ since a logic

“low” on this line would cause the input amplifiers to run

open-loop.

Other gains may be set by connecting an external resistor,

R

gain-setting resistor is a function of R

20k

Ω resistors. The internal resistors are typically within

±0.2% of nominal value and their drift under ±80ppm/°C.

Inaccuracy and drift of R

error and drift.

Figure 3b shows an external gain-setting resistor connected

in parallel with internal resistors. By forming a portion of the

effective R

can be somewhat improved.

Connections available on the INA120 allow all input stage

gain-setting resistors to be provided externally. A custom

precision resistor network could be connected to provide the

highest accuracy and lowest gain drift for non-standard

gains. Impedance of this external network should be made

close to that of the internal network for best performance.

OFFSET TRIMMING

Many applications require no external offset voltage trim-

ming. Figure 4 shows optional circuits for trimming offset

voltage. Since the INA120 has two amplification stages, the

offset voltage is comprised of two components—the input

stage offset and output stage offset.

The input stage offset is equal to the combined offset of op

amps A

gain. When used in gains of 100 to 1000, it is often

sufficient to adjust the input stage offset with a potentiome-

ter connected to pins 6 and 7 as shown. Connect both inputs

to ground and adjust for 0V at the output, pin 1. Do not use

pins 6 and 7 to trim offset voltage at G = 1 or to correct for

offset in devices following the INA120 since this can cause

excessive offset voltage drift.

At G = 1, offset is dominated by the output stage. Output

stage offset can be trimmed by applying a correction voltage

at the output reference terminal, pin 18. Low impedance

must be maintained at this node to preserve the high CMR

of the INA120. This is achieved by buffering the trim

voltage with an op amp as shown.

At intermediate gains it may be necessary to provide both

input stage and output stage offset adjustments. Again,

ground both inputs. Connect a jumper between pins 9 and 11

(temporarily connects the INA120 in high gain) and adjust

R

and adjust the output offset control for 0V output.