DP7269 datasheet(8/16 Pages) COPAL

8 / 16 page

DP7269

Doc. No. MD-2123 Rev. D

NIDEC COPAL ELECTRONICS CORP.

Characteristics subject to change without notice

INSTRUCTION AND REGISTER

DESCRIPTION

SLAVE ADDRESS BYTE

The

first

byte

sent

the

DP7269

from

the

master/processor is called the Slave/DP Address

Byte. The most significant four bits of the slave

address are a device type identifier. These bits for the

DP7269 are fixed at 0101[B] (refer to Table 1).

The next four bits, A3 - A0, are the internal slave

address and must match the physical device address

which is defined by the state of the A3 - A0 input pins

for

the

DP7269

successfully

continue

the

command sequence. Only the device which slave

address matches the incoming device address sent by

the master executes the instruction. The A3 - A0

inputs can be actively driven by CMOS input signals

or tied to VCC or VSS.

INSTRUCTION BYTE

The next byte sent to the DP7269 contains the

instruction and register pointer information. The four

most significant bits used provide the instruction

opcode I3 - I0. The R1 and R0 bits point to one of the

four data registers of each associated potentiometer.

The least two significant bits point to one of four Wiper

Control Registers. The format is shown in Table 2.

Data Register Selection

Data Register Selected

DR0

DR1

Figure 6. Write Timing

Table 1. Identification Byte Format

Table 2. Instruction Byte Format

DR1 WCRDATA

BUS ACTIVITY:

MASTER

SDA LINE

SLAVE/DP

ADDRESS

INSTRUCTION

BYTE

Fixed

Variable

op code

Address

Pot1 WCR

Address

ID3

ID2

ID1

ID0

0101

(MSB)

(LSB)

Device Type

Identifier

Slave Address

(MSB)

(LSB)

Instruction

Data Register

WCR/Pot Selection

Opcode

Selection

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