MCP9902 datasheet(32/50 Pages) MICROCHIP

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MCP9902/3/4

DS20005382C-page 32

 2015-2016 Microchip Technology Inc.

CONSEC ALERT – CONSECUTIVE ALERT REGISTER (ADDRESS 22H)

RW-0

RW-1

RW-0

U-0

TMOUT

CTHM<2:0>

CALRT<2:0>

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

-n = Value at POR

‘1’ = bit is set

‘0’ = Bit is cleared

x = Bit in unknown

TMOUT

: Enables the time-out and idle functionality of the I2C protocol

= The I2C time-out and idle functionality are enabled. The I2C interface will time-out if the clock line

is held low for longer than 30 ms. Likewise, it will reset if both the data and clock lines are held high for

longer than 200 µs.

= The I2C time-out and idle functionality are disabled. The I2C interface will not time-out if the clock

line is held low for longer than 30ms. Likewise, it will not reset if both the data and clock lines are held

high for longer than 200 µs. This is used for I2C compliance.

6-4

CTHM<2:0>

: Determines the number of consecutive measurements that must exceed the

corresponding Therm Limit before the THERM pin is asserted

000

= 1

001

= 2

011

= 3

111

= 4

3-1

CALRT<2:0>

: Determines the number of consecutive measurements that must exceed the

corresponding Therm Limit before the ALERT/THERM2 pin is asserted

000

= 1

001

= 2

011

= 3

111

= 4

Unimplemented

: Read as ‘0’

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