TUSB8040PFPR datasheet(12/32 Pages) TI1

12 / 32 page

Not Recommended for New Designs

TUSB8040

SLLSE42I – SEPTEMBER 2010 – REVISED SEPTEMBER 2013

www.ti.com

Table 2-5. Test and Miscellaneous Signals (continued)

SIGNAL NAME

TYPE

PIN NO.

DESCRIPTION

Full power management enable/SMBus address bit 1.

The value of the terminal is sampled at the de-assertion of reset to set the power switch

control follows:

0 = Full power management supported

FULLPWRMGMTz_S

1 = Full Power management not supported

I, PU

MBA1

Full power management is the ability to control power to the downstream ports of the

TUSB8040 using the PWRON0z_BATEN0 terminal. When SMBus mode is enabled using

SMBUSz, this terminal sets the value of the SMBus slave address bit 1. SMBus slave

address bits 2 and 3 are always 1 for the TUSB8040.

Can be left unconnected if full power management and SMBus are not implemented.

2.6

Power Signals

Table 2-6. Power Signals

SIGNAL NAME

TYPE

PIN NO.

DESCRIPTION

4, 19, 21,

38, 43, 58

VDD33

3.3-V power rail

68, 72, 77,

1, 5, 10,

11, 16, 20,

26, 32, 37,

VDD11

1.1-V power rail

42, 46, 51,

52, 57, 61,

67, 71

GND

64, 81

Ground, Power Pad

PIN DESCRIPTIONS

Submit Documentation Feedback

Product Folder Links: TUSB8040

TUSB8040PFPR Datasheet(PDF) 12 Page - Texas Instruments

TUSB8040PFPR Datasheet(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL