SN10501DBVR datasheet(15/23 Pages) TI

15 / 23 page

SN10501

SN10502

SN10503

SLOS408A − MARCH 2003 − REVISED DECEMBER 2003

www.ti.com

BOARD LAYOUT

Achieving optimum performance with a high frequency

amplifier like the SN1050x requires careful attention to

board layout parasitics and external component types.

Recommendations that will optimize performance include:

Minimize parasitic capacitance to any ac ground

for all of the signal I/O pins. Parasitic capacitance on

the output and inverting input pins can cause

instability: on the noninverting input, it can react with

the source impedance to cause unintentional band

limiting. To reduce unwanted capacitance, a window

around the signal I/O pins should be opened in all of

the ground and power planes around those pins.

Otherwise, ground and power planes should be

unbroken elsewhere on the board.

Minimize the distance (< 0.25”) from the power

supply pins to high frequency 0.1-

µF decoupling

capacitors. At the device pins, the ground and power

plane layout should not be in close proximity to the

signal I/O pins. Avoid narrow power and ground traces

to minimize inductance between the pins and the

decoupling capacitors. The power supply connections

should always be decoupled with these capacitors.

Larger (2.2-

µF to 6.8-µF) decoupling capacitors,

effective at lower frequency, should also be used on

the main supply pins. These may be placed somewhat

farther from the device and may be shared among

several devices in the same area of the PC board.

Careful selection and placement of external

components

preserves

the

high

frequency

performance of the SN1050x. Resistors should be a

very low reactance type. Surface-mount resistors

work best and allow a tighter overall layout. Metal-film

and carbon composition, axially-leaded resistors can

also provide good high frequency performance.

Again, keep their leads and PC board trace length as

short as possible. Never use wire wound type

resistors in a high frequency application. Since the

output pin and inverting input pin are the most

sensitive to parasitic capacitance, always position the

feedback and series output resistor, if any, as close as

possible to the output pin. Other network components,

such as noninverting input termination resistors,

should also be placed close to the package. Where

double-side component mounting is allowed, place

the feedback resistor directly under the package on

the other side of the board between the output and

inverting input pins. Even with a low parasitic

capacitance

shunting

the

external

resistors,

excessively high resistor values can create significant

time constants that can degrade performance. Good

axial metal-film or surface-mount resistors have

approximately 0.2 pF in shunt with the resistor. For

resistor values > 2.0 k

Ω, this parasitic capacitance can

add a pole and/or a zero below 400 MHz that can

effect circuit operation. Keep resistor values as low as

possible, consistent with load driving considerations.

It has been suggested that a good starting point for

design is to set the Rf to 1.3 kΩ for low-gain,

noninverting applications. Doing this automatically

keeps the resistor noise terms low, and minimizes the

effect of their parasitic capacitance.

Connections to other wideband devices on the

board may be made with short direct traces or

through onboard transmission lines. For short

connections, consider the trace and the input to the

next device as a lumped capacitive load. Relatively

wide traces (50 mils to 100 mils) should be used,

preferably with ground and power planes opened up

around them. Estimate the total capacitive load and

set RISO from the plot of recommended RISO vs

Capacitive Load. Low parasitic capacitive loads

(<4 pF) may not need an R(ISO), since the SN1050x is

nominally compensated to operate with a 2-pF

parasitic load. Higher parasitic capacitive loads

without an R(ISO) are allowed as the signal gain

increases (increasing the unloaded phase margin). If

a long trace is required, and the 6-dB signal loss

intrinsic to a doubly-terminated transmission line is

acceptable,

implement

matched

impedance

transmission

line

using

microstrip

stripline

techniques (consult an ECL design handbook for

microstrip and stripline layout techniques). A 50-

Ω

environment is normally not necessary onboard, and

in fact a higher impedance environment improves

distortion as shown in the distortion versus load plots.

With a characteristic board trace impedance defined

based on board material and trace dimensions, a

matching series resistor into the trace from the output

of the SN1050x is used as well as a terminating shunt

resistor at the input of the destination device.

Remember also that the terminating impedance is the

parallel combination of the shunt resistor and the input

impedance of the destination device: this total

effective impedance should be set to match the trace

impedance. If the 6-dB attenuation of a doubly

terminated transmission line is unacceptable, a long

trace can be series-terminated at the source end only.

Treat the trace as a capacitive load in this case and set

the series resistor value as shown in the plot of R(ISO)

vs Capacitive Load. This setting does not preserve

signal integrity or a doubly-terminated line. If the input

impedance of the destination device is low, there is

some signal attenuation due to the voltage divider

formed by the series output into the terminating

impedance.

SN10501DBVR Datasheet(PDF) 15 Page - Texas Instruments

SN10501DBVR Datasheet(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL