ST7MC2 datasheet(217/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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MOTOR CONTROLLER (Cont’d)

PWM CONTROL REGISTER (MPCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = PMS: PWM Mode Selection.

0: Standard mode: bit b7 in the MCPxH register

represents the extension bit.

1: “8-bit” mode: bit b7 (extension bit) in the MCPxH

bits); the number of active bits in MCPxH and

MCPxL is decreased to b15:b8 instead of

b15:b3.

Bit 6 = OVFU: Phase U 100% duty cycle Selec-

tion.

0: Duty cycle defined by MCPUH:MCPUL register.

1: Duty cycle set at 100% on phase U at next up-

date event and maintained till the next one. This

bit is reset once transferred to the active register

on update event.

Bit 5 = OVFV: Phase V 100% duty cycle Selection.

0: Duty cycle defined by MCPVH:MCPVL register.

1: Duty cycle set at 100% on phase V at next up-

date event and maintained till the next one. This

bit is reset once transferred to the active register

on update event.

Bit 4 = OVFW: Phase W 100% duty cycle Selec-

tion.

0: Duty cycle defined by MCPWH:MCPWL regis-

ter.

1: Duty cycle set at 100% on phase W at next up-

date event and maintained till the next one. This

bit is reset once transferred to the active register

on update event.

Bit 3 = CMS: PWM Counter Mode Selection.

0: Edge-aligned mode

1: Center-aligned mode

Bits 2:0 = PCP[2:0] PWM counter prescaler value.

This value divides the Fmtc frequency by N, where

N is PCP[2:0] value. Table 73 shows the resulting

frequency of the PWM counter input clock.

Table 73. PWM clock prescaler

PMS

OVFU OVFV OVFW

CMS

PCP2

PCP1

PCP0

PCP2

PCP1

PCP0

PWM counter input clock

Fmtc

Fmtc/2

Fmtc/3

Fmtc/4

Fmtc/5

Fmtc/6

Fmtc/7

Fmtc/8

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