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ST7MC2 Datasheet(PDF) 221 Page - STMicroelectronics |
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ST7MC2 Datasheet(HTML) 221 Page - STMicroelectronics |
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221 / 308 page ![]() ST7MC1/ST7MC2 221/308 MOTOR CONTROLLER (Cont’d) POLARITY REGISTER (MPOL) Read/Write (some bits write-once) Reset Value: 0011 1111 (3Fh) Bit 7 = ZVD: Z vs D edge polarity. 0: Zero-crossing and End of Demagnetisation have opposite edges 1: Zero-crossing and End of Demagnetisation have same edge Bit 6 = REO: Read on High or Low channel bit 0: Read the BEMF signal on High channels 1: Read on Low channels Note: This bit always has to be configured whatev- er the sampling method. Bits 5:0 = OP[5:0]*: Output channel polarity. These bits are used together with the OO[5:0] bits in the MPHST register to control the output chan- nels. 0: Output channel is Active Low 1: Output channel is Active High. * Write-once bits; once write-accessed these bits cannot be re-written unless the processor is reset (See “Caution: Access to write-once bits” on page 219.). Table 75. Output Channel State Control Warning: OP[5:0] bits in the MPOL register must be configured as required by the application be- fore enabling the MCO[5:0] outputs with the MOE bit in the MCRA register. 76 54 32 10 ZVD REO OP5 OP4 OP3 OP2 OP1 OP0 OP[5:0] bit OO[5:0] bit MCO[5:0] pin 00 1 (Off) 0 1 0 (PWM possible) 10 0 (Off) 1 1 1 (PWM possible) |
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