LTC4355 datasheet(16/24 Pages) LINEAR

16 / 24 page

LTC4420

4420f

For more information www.linear.com/LTC4420

applicaTions inForMaTion

Reverse Voltage Blocking

The LTC4420 blocks reverse voltages on supply pins V1

and V2 up to –15V relative to GND and up to –39V relative

to OUT. Transient voltage suppressors (TVS) connected to

V1 and V2 must be bidirectional and capacitors connected

to these pins must be rated to handle reverse voltages. A

reverse voltage on V2 does not disrupt V1 operation and

vice-versa.

Freshness Seal Mode

Freshness seal mode prevents V2 battery discharge by

keeping V2 disconnected from OUT even if V1 is absent

or invalid. Very little current is drawn from V2—typically

just 120nA. The following sequence (refer to Figure 10)

puts the LTC4420 in freshness seal mode:

1. Power up V2 and V2UV.

2. Once V2OK is asserted high, drive it below 50mV.

3. Power up V1 and ADJ for at least 94ms. Complete steps

2 and 3 within 80s of V2OK asserting high. Freshness

seal is enabled.

Figure 9. Voltage Waveforms When a Brownout on V1

Results in Switchover to V2. Switchover Threshold = 3V

Figure 8. Voltage Waveforms During a Brownout on V1

That Does Not Result in Switchover to V2. Switchover

Threshold = 1.8V

Figure 10. Freshness Seal Engage Procedure

COUT = 10µF

ROUT = 100Ω

100µs/DIV

5V/DIV

OUT

5V/DIV

4420 F08

100µs/DIV

5V/DIV

OUT

5V/DIV

4420 F09

COUT = 10µF

ROUT = 100Ω

Engage this mode if V2 is a backup battery either during

storage or during shipment. Once freshness seal has been

engaged, if V1 is disconnected, V2 stays disconnected

from OUT. Freshness seal is automatically disabled the

next time V1 is revalidated. Limit V2OK pin capacitance

to less than 10nF in order to prevent freshness seal mode

from accidentally being engaged.

Design Example

In Figure 11, the LTC4420 prioritizes between a 5V supply

connected to V1 and a 7.4V 2-cell Li-Ion battery con-

nected to V2. The system is designed to switch OUT to

V2 when V1 drops below 4V, provide early power failure

warning when V1 drops below 4.5V and disconnect the

backup battery voltage when it drops below 6V. Maximum

anticipated load current is 100mA and maximum allowed

outputdroopis100mV.Outputrisingslewrateislimitedto

<0.1V/µs and V1 and V2 input capacitances are limited to

10µF to avoid large inrush current. 1% tolerance resistors

are used ADJ, CMP1 and V2UV pin leakages and GNDSW

VOL are ignored as their design impact is small.

V2UV

V2OK

ADJ

1.8V

0.48V

1.8V

1.116V

4420 F10

94ms

FSEAL

ENABLED

DRIVEN LOW

EXTERNALLY

< 80s

LTC4355 Datasheet(PDF) 16 Page - Linear Integrated Systems

LTC4355 Datasheet(HTML) 16 Page - Linear Integrated Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL