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STLC2410B Datasheet(PDF) 16 Page - STMicroelectronics |
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STLC2410B Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 20 page  STLC2410B 16/20 The four signals of the PCM interface are: – PCM_CLK : PCM clock – PCM_SYNC : PCM 8kHz sync – PCM_A : PCM data – PCM_B : PCM data Directions of PCM_A and PCM_B are software configurable. Figure 5. PCM (A-law, µ-law) standard mode Figure 6. Linear mode Table 10. PCM interface timing. Symbol Description Min Typ Max Unit PCM Interface Fpcm_clk Frequency of PCM_CLK (master) - 2048 kHz Fpcm_sync Frequency of PCM_SYNC 8 kHz tWCH High period of PCM_CLK 200 ns tWCL Low period of PCM_CLK 200 ns tWSH High period of PCM_SYNC 200 ns tSSC Setup time, PCM_SYNC high to PCM_CLK low 100 ns tSDC Setup time, PCM_A/B input valid to PCM_CLK low 100 ns tHCD Hold time, PCM_CLK low to PCM_A/B input invalid 100 ns tDCD Delay time, PCM_CLK high to PCM_A/B output valid 150 ns D02TL558 PCM_CLK PCM_SYNC PCM_A B B PCM_B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B 125 µs B D02TL559 PCM_CLK PCM_SYNC PCM_A PCM_B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 125 µs |
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