TAS5036 datasheet(3/49 Pages) TI

3 / 49 page

Contents

November 2002

SLES044B

Contents

Section

Page

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2

Functional Block Diagram . . . . . . . . . . . . .

1.3

Terminal Assignments . . . . . . . . . . . . . . . .

1.4

Ordering Information . . . . . . . . . . . . . . . . .

1.5

Terminal Functions . . . . . . . . . . . . . . . . . . .

Architecture Overview . . . . . . . . . . . . . . . . . . . . .

2.1

Clock and Serial Data Interface . . . . . . . .

2.1.1

Normal-Speed, Double-Speed,

and Quad-Speed Selection . .

2.1.2

Clock Master/Slave Mode

(M_S) . . . . . . . . . . . . . . . . . . . .

2.1.3

Clock Master Mode . . . . . . . . .

2.1.4

Clock Slave Mode . . . . . . . . . .

2.1.5

PLL Filter . . . . . . . . . . . . . . . . .

2.1.6

DCLK . . . . . . . . . . . . . . . . . . . . .

2.1.7

Serial Data Interface . . . . . . . .

2.2

Reset, Power Down, and Status . . . . . . .

2.2.1

Reset—RESET . . . . . . . . . . . .

2.2.2

Power Down—PDN . . . . . . . .

2.2.3

Status Registers . . . . . . . . . . .

2.3

Signal Processing . . . . . . . . . . . . . . . . . . .

2.3.1

Volume Control . . . . . . . . . . . .

2.3.2

Mute . . . . . . . . . . . . . . . . . . . . .

2.3.3

Auto Mute . . . . . . . . . . . . . . . . .

2.3.4

Individual Channel Mute . . . . .

2.3.5

De-Emphasis Filter . . . . . . . . .

2.4

Pulse Width Modulator (PWM) . . . . . . . . .

2.4.1

Clipping Indicator . . . . . . . . . . .

2.4.2

Error Recovery . . . . . . . . . . . .

2.4.3

Individual Channel Error Re-

covery . . . . . . . . . . . . . . . . . . . .

2.4.4

PWM DC-Offset Correction . .

2.4.5

Inter-Channel Delay . . . . . . . .

2.4.6

ABD Delay . . . . . . . . . . . . . . . .

2.4.7

PWM/H-Bridge and Discrete

H-Bridge Driver Interface . . . .

2.5

I2C Serial Control Interface . . . . . . . . . . .

2.5.1

Single Byte Write . . . . . . . . . . .

2.5.2

Multiple Byte Write . . . . . . . . .

2.5.3

Single Byte Read . . . . . . . . . . .

2.5.4

Multiple Byte Read . . . . . . . . .

Serial Control Interface Register Definitions .

3.1

General Status Register (x00) . . . . . . . . .

3.2

Error Status Register (x01) . . . . . . . . . . . .

3.3

System Control Register 0 (x02) . . . . . . .

3.4

System Control Register 1 (x03) . . . . . . .

3.5

Error Recovery Register (x04) . . . . . . . . .

3.6

Automute Delay Register (x05) . . . . . . . .

3.7

DC-Offset Control Registers (x06–x0B) .

3.8

Interchannel Delay Registers (x0C–x11)

3.9

ABD Delay Register (x12) . . . . . . . . . . . . .

3.10

Individual Channel Mute Register (x19) .

System Initialization . . . . . . . . . . . . . . . . . . . . . . .

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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