LM13700 datasheet(18/24 Pages) NSC

18 / 24 page

Additional Applications (Continued)

Figure 23 shows a Tachometer or Frequency-to-Voltage con-

verter. Whenever A1 is toggled by a positive-going input, an

amount of charge equal to (V

H–VL)Ct is sourced into Cf and

t. This once per cycle charge is then balanced by the cur-

rent of V

O/Rt. The maximum FIN is limited by the amount of

time required to charge C

t from VL to VH with a current of IB,

where V

L and VH represent the maximum low and maximum

high output voltage swing of the LM13700. D1 is added to

provide a discharge path for C

t when A1 switches low.

The Peak Detector of

Figure 24 uses A2 to turn on A1 when-

ever V

IN becomes more positive than VO. A1 then charges

storage capacitor C to hold V

O equal to VIN PK. Pulling the

output of A2 low through D1 serves to turn off A1 so that V

remains constant.

The Ramp-and-Hold of

Figure 26 sources I

B into capacitor C

whenever the input to A1 is brought high, giving a ramp-rate

of about 1V/ms for the component values shown.

The true-RMS converter of

Figure 27 is essentially an auto-

matic gain control amplifier which adjusts its gain such that

the AC power at the output of amplifier A1 is constant. The

output power of amplifier A1 is monitored by squaring ampli-

fier A2 and the average compared to a reference voltage

with amplifier A3. The output of A3 provides bias current to

the diodes of A1 to attenuate the input signal. Because the

output power of A1 is held constant, the RMS value is con-

stant and the attenuation is directly proportional to the RMS

value of the input voltage. The attenuation is also propor-

tional to the diode bias current. Amplifier A4 adjusts the ratio

of currents through the diodes to be equal and therefore the

voltage at the output of A4 is proportional to the RMS value

of the input voltage. The calibration potentiometer is set such

that V

O reads directly in RMS volts.

DS007981-30

FIGURE 23. Tachometer

DS007981-31

FIGURE 24. Peak Detector and Hold Circuit

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