ADS5204IPFB datasheet(6/18 Pages) TI

6 / 18 page

ADS5204

SBAS268A – JUNE 2002 – REVISED JULY 2002

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TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input Clock Rate

fCLK

MHz

Conversion Rate

MSPS

Clock Duty Cycle (40MHz)

Clock Duty Cycle (80MHz)

Output Delay Time

td(o)

CL = 10pF

Mux Setup Time

ts(m)

10.4

Mux Hold Time

th(m)

CL = 10pF

1.7

2.1

Output Setup Time

ts(o)

CL = 10pF

10.4

Pipeline Delay (latency, channels A and B)

td(pipe)

MODE = 0, SELB = 0

CLK Cycles

Pipeline Delay (latency, channels A and B)

td(pipe)

MODE = 1, SELB = 0

CLK Cycles

Pipeline Delay (latency, channel A)

td(pipe)

MODE = 0, SELB = 1

CLK Cycles

Pipeline Delay (latency, channel B)

td(pipe)

MODE = 0, SELB = 1

CLK Cycles

Pipeline Delay (latency, channel A)

td(pipe)

MODE = 1, SELB = 1

CLK Cycles

Pipeline Delay (latency, channel B)

td(pipe)

MODE = 1, SELB = 1

CLK Cycles

Output Hold Time

th(o)

CL = 10pF

1.5

2.2

Aperture Delay Time

td(a)

Aperture Jitter

tJ(a)

1.5

ps, rms

Disable Time, OE Rising to Hi–Ztdis

Enable Time, OE Falling to Valid Data

ten

(1) All internal operations are performed at a 40MHz clock rate.

SERIAL INTERFACE TIMING

PARAMETER

MIN

TYP

MAX

UNIT

Maximum Clock Rate

fSCLK

MHz

SCLK Pulse Width HIGH

tWH

SCLK Pulse Width LOW

tWH

Setup Time, CS LOW Before First Negative SCLK Edge

tSU(CS_CK)

CS HIGH Width

tWH(CS)

Setup Time, 16th Negative SCLK Edge before CS Rising Edge

tSU(C16_CK)

Setup Time, Data Ready Before SCLK Falling Edge

tSU(D)

Hold Time, Data Held Valid After SCLK Falling Edge

tSU(H)

TIMING OPTIONS

OPERATING MODE

MODE

SELB

TIMING DIAGRAM FIGURE

80MHz Input Clock, Dual-Bus Output, COUT = 40MHz

40MHz Input Clock, Dual-Bus Output, COUT = 40MHz

80MHz Input Clock, Single-Bus Output, COUT = 40MHz

80MHz Input Clock, Single-Bus Output, COUT = 80MHz

ADS5204IPFB Datasheet(PDF) 6 Page - Texas Instruments

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