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CDCVF2310 Datasheet(PDF) 7 Page - Texas Instruments |
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CDCVF2310 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 11 page ![]() www.ti.com SWITCHING CHARACTERISTICS VDD = 3.3 V ±0.3 V (SEE FIGURE 2) VDD = 2.5 V ±0.2 V (SEE FIGURE 2) PARAMETER MEASUREMENT INFORMATION 500 Ω CL = 25 pF on Yn From Output Under Test CDCVF2310 SCAS666B – JUNE 2001 – REVISED JANUARY 2004 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH f = 0 MHz to 200 MHz CLK to Yn 1.3 2.8 ns For circuit load, see Figure 2. tPHL tsk(o) Output skew (Ym to Yn) (1) (see Figure 4) 100 ps tsk(p) Pulse skew (see Figure 5) 250 ps tsk(pp) Part-to-part skew 500 ps tr Rise time (see Figure 3) VO = 0.4 V to 2 V 0.7 2 V/ns tf Fall time (see Figure 3) VO = 2 V to 0.4 V 0.7 2 V/ns tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns th(en) Enable hold time, G_high after CLK ↓ 0.4 ns th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns (1) The tsk(o) specification is only valid for equal loading of all outputs. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH f = 0 MHz to 170 MHz CLK to Yn 1.5 3.5 ns For circuit load, see Figure 2. tPHL tsk(o) Output skew (Ym to Yn) (1) (see Figure 4 ) 170 ps tsk(p) Pulse skew (see Figure 5) 400 ps tsk(pp) Part-to-part skew 600 ps tr Rise time (see Figure 3) VO = 0.4 V to 1.7 V 0.5 1.4 V/ns tf Fall time (see Figure 3) VO = 1.7 V to 0.4 V 0.5 1.4 V/ns tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns th(en) Enable hold time, G_high after CLK ↓ 0.4 ns th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns (1) The tsk(o) specification is only valid for equal loading of all outputs. A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, Z O = 50 Ω, tr < 1.2 ns, tf < 1.2 ns. Figure 2. Test Load Circuit 7 |
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