COM20022ITQFP datasheet(61/83 Pages) SMSC

61 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 61

Rev. 08-18-03

DATASHEET

Figure 8.2

- Multiplexed Bus, 80XX-Like Control Signals; Read Cycle

ALE High Width

ALE Low Width

nRD Low Width

nRD High Width

nWR

to nRD Low

nIOCS16 Hold Delay from ALE Low

nIOCS16 Output Delay from ALE Low

AD0-AD2,

VALID

nCS

ALE

VALID DATA

t2,

D3-D15

nRD

t10

nWR

t13

t11

t12

nIOCS16

Previous Value

Invalid

Valid Value

t15

t14

Note 3

Note 2

Parameter

min

max

units

t10

t11

t12

t13

t14

t15

Address Setup to ALE Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nRD Low

nRD Low to Valid Data

nRD High to Data High Impedance

Cycle Time (nRD Low to Next Time Low)

4TARB

MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0

The Microcontroller typically accesses the COM20022 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20022 cycles.

Note 1:

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from

Data Register requires a minimum of 5TARB from the trailing edge of nRD to the

leading edge of the next nRD.

Notes 2 and 3 are applied to an access to Data Register by DMA transfer.

Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to

Data Register requires a minimum of 5TARB from the trailing edge of nWR to the

leading edge of nRD.

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