MEMS Oscillator, High Temperature, LVCMOS/HCMOS Compatible, 115.19401 MHz to 137.000MHz

IM821 Series

ILSI America Phone 775-851-8880 ● Fax 775-851-8882 ●email: e-mail@ilsiamerica.com ●

www.ilsiamerica.com

Specifications subject to change without notice

Rev 01/30/16_A

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Features:



MEMS Technology



Direct pin to pin drop-in replacement for industry-standard packages



LVCMOS/HCMOS Compatible Output



Industry-standard package 2.0 x1.6, 2.5 x 2.0, 3.2 x 2.5, and 5.0 x 3.2 mm x mm



Pb-free, RoHS and REACH compliant



Fast delivery times

Typical Applications:



Fibre Channel



Server and Storage



GPON, EPON



100M / 1G /10G Ethernet

Electronic Specifications:

Frequency Range

115.194001 MHz to 137.000MHz

Frequency Stability

See Part Number Guide

Inclusive of Initial Tolerance, Operating Temperature Range, Load, Voltage,

and Aging

Operating Temperature

See Part Number Guide

Supply Voltage (Vdd) ±10%

See Part Number Guide

Current Consumption

6.2 mA typ./ 8.0 mA max

5.4 mA typ./ 7.0 mA max

4.9 mA typ./ 6.0 mA max

No load condition, F = 125 MHz, Vdd = +2.8 V, +3.0 V or +3.3 V

No load condition, F = 125 MHz, Vdd = +2.5 V

No load condition, F = 125 MHz, Vdd = +1.8 V

OE Disable Current

4.7 mA max

4.5 mA max

Vdd = +2.5 V, or +3.3 V, OE = Low, output is high Z state

Vdd = +1.8 V, OE = Low, output is high Z state

Standby Current

2.6 µA typ./ 8.5 µA max

1.4 µA typ./ 5.5 µA max

0.6 µA typ./ 4.0 µA max

Vdd = +2.8 V to 3.3 V,

ST = low

Vdd = +2.5 V,

ST = Low

Vdd = +1.8 V,

ST = Low

Waveform Output

LVCMOS/HCMOS

Symmetry

45%/55%

50% of waveform

Rise / Fall Time

1.0 nSec typ./ 2.0 nSec max

1.3 nSec typ./ 2.5 nSec max

Vdd = +2.5 V, +2.8 V, 3.0 V or 3.3 V from 20% to 80% of waveform

Vdd = +1.8 V, from 20% to 80% of waveform

Logic “1”

90% of Vdd min

Logic “0”

10% of Vdd max

Input Voltage High

70% of Vdd min

Pin 1, OE or

ST

Input Voltage Low

30% of Vdd max

Pin 1, OE or

ST

Input Pull-up Impedance

50 kΩ min / 87 kΩ typ./ 150 kΩ max

2.0 MΩ min

Pin 1, OE logic high or logic low, or

ST logic high

Pin 1,

ST logic low

Startup Time

5 mSec max

Measured from the time Vdd reaches its rated minimum values

Enable/Disable Time

130 nSec max

F = 115.194001 MHz, For other frequencies, T_oe = 100 nSec + 3 * clock

periods

Resume Time

5 mSec max

Measured from the time

ST pin crosses 50% threshold.

RMS Period Time

1.6 pSec typ./ 2.5 pSec max

1.8 pSec typ./ 3.0 pSec max

F = 125 MHz, Vdd = +2.5 V, +2.8 V, +3.0 V or +3.3 V

F = 125 MHz, Vdd = +1.8 V

Peak-to-Peak Period Jitter

12 pSec typ./ 20 pSec max

14 pSec typ./ 30 pSec max,

F = 125 MHz, Vdd = +2.5 V, +2.8 V, +3.0 V or +3.3 V

F = 125 MHz, Vdd = +1.8 V

RMS Period Time (random)

0.5 pSec typ./ 0.8 pSec max,

1.3 pSec typ./ 2.0 pSec max,

F = 125 MHz, Integration bandwidth = 900 kHz to 7.5 MHz

F = 125 MHz, Integration bandwidth = 12.0 kHz to 20.0 MHz

Notes:



All min and max limits are specified over temperature and rated operating voltage with 15pF output unless otherwise stated.



Typical values are at +25ºC and nominal supply voltage.