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ICS83840 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS83840 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 8 page  83840AH www.icst.com/products/hiperclocks.html REV. A DECEMBER 22, 2003 1 Integrated Circuit Systems, Inc. ICS83840 DDR SDRAM MUX GENERAL DESCRIPTION The ICS83840 is a DDR SDRAM MUX and is a member of the HiPerClock S™ family of High Performance Clock Solutions from ICS. The device has 10 Host Lines and each host line can be passed to 4 Data Ports. The 10 channels are allocated as follows in the DDR SDRAM application: 8 data lines, 1 strobe line and 1 DQm line. The Host/Data Ports are compatible with single-ended SSTL-2 and the device oper- ates from a 2.5V supply. Guaranteed low output skew makes the ICS83840 ideal for demanding applications which require well defined perfor- mance and repeatability. LOGIC DIAGRAM FEATURES • 40 low skew single-ended DIMM ports • 4 SSTL-2 compatible enable inputs • Maximum Switching Speed: 3ns • Output skew: 120ps (maximum) • Bank skew: 45ps (maximum) • r on = 8 Ω (typical) • Full 2.5V supply modes • 0°C to 70°C ambient operating temperature • Pin compatible with the CBTV4010 HiPerClockS™ ICS SIMPLIFIED SCHEMATIC HPx nSn nDPx SW 400 Ω HP0 0DP0 1DP0 2DP0 3DP0 HP9 Sw Sw Sw Sw 0DP9 1DP9 2DP9 3DP9 Sw Sw Sw Sw nS0 nS1 nS2 nS3 RON RON ICS83840 64-Ball TFBGA 7mm x 7mm x 1.2mm package body H Package Top View PIN ASSIGNMENT V D D 1 S nc n0 P D 10 P D 20 P D 31 P D 21 P D 32 P D 0 2 S nV D D 0 S nD N G0 P D 00 P H1 P D 01 P D 11 P HD N G2 P D 1 c n3 S n 2 P H2 P D 2 D N G 2 P D 3 9 P D 29 P D 3 3 P D 03 P D 1 9 P D 19 P H 3 P H3 P D 2 9 P D 08 P D 3 D N G3 P D 3 8 P D 2 4 P D 0 8 P D 18 P H 4 P H4 P D 1 8 P D 0D N G7 P H7 P D 06 P D 36 P HD N G5 P D 35 P H4 P D 34 P D 2 7 P D 37 P D 27 P D 16 P D 26 P D 16 P D 05 P D 25 P D 15 P D 0 1 2 34 5 6 789 10 11 A B C D E F G H J K L |
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