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SN65472DREP Datasheet(PDF) 3 Page - Texas Instruments

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Part # SN65472DREP
Description  DUAL PERIPHERAL DRIVER
PDF  13 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65472DREP Datasheet(HTML) 3 Page - Texas Instruments

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SN65472-EP
www.ti.com
SLRS061 – SEPTEMBER 2013
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range(2)
7
V
VI
Input voltage
5.5
V
Inter-emitter voltage(3)
5.5
V
VO
Off-state output voltage
70
V
IO
Continuous collector or output current(4)
400
mA
Peak collector or output current (tw ≤ 10 ms, duty cycle ≤ 50%)
(4)
500
mA
TJ
Absolute maximum junction temperature range
–40
150
°C
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Voltage values are with respect to the network GND, unless otherwise specified.
(3)
This is the voltage between two emitters, A and B.
(4)
Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time
interval must fall within the continuous dissipation rating.
THERMAL INFORMATION
SN65472-EP
THERMAL METRIC(1)
D
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance(2)
115.3
θJCtop
Junction-to-case (top) thermal resistance(3)
59.7
θJB
Junction-to-board thermal resistance(4)
56.2
°C/W
ψJT
Junction-to-top characterization parameter(5)
13.5
ψJB
Junction-to-board characterization parameter(6)
55.6
θJCbot
Junction-to-case (bottom) thermal resistance(7)
N/A
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.75
5
5.25
V
VIH
High-level input voltage
2.1
V
VIL
Low-level input voltage
0.8
V
TA
Operating free-air temperature range
-40
85
°C
TJ
Operating virtual junction temperature
-40
125
°C
Copyright © 2013, Texas Instruments Incorporated
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