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SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
RF I/O Description
The SiW3000 processor employs single-ended RF input and output pins for reduced external components. In typical
Class-2 (0 dBm nominal) applications, simple LC network matching circuits will be required to combine the two ports into
a single antenna port and provide impedance matching. Please refer to the RF impedance table and the application cir-
cuits for values and matching circuit examples. The SiW3000 can be used to design Class-1 (+20 dBm) products with
the addition of power amplifier circuits. Control signals are available to facilitate the design of the external PA circuit.
Reset
The SiW3000 processor can be reset by asserting the RESET_N signal to the chip (active low). Upon applying power,
the RESET_N must be asserted until voltage supply and internal voltage regulators have stabilized. A simple RC circuit
can be used to provide the power-on reset signal to the SiW3000.
On-Chip Memory
The SiW3000 Radio Processor integrates both SRAM and ROM. The ROM is pre-programmed with Bluetooth protocol
stack software (HCI software) and boot code that executes automatically upon reset. The boot code serves to control the
boot sequence as well as to direct the execution to the appropriate memory for continued operation.
Configuration Selection
HCI Transport Interface Selection
The HCI transport (USB or UART) is selected on power up by sampling PIO2. If UART is selected, the selection of the
particular UART transport (H:4 or H:5) is performed automatically by the software.
Reference Frequency Selection
The SiW3000 radio processor is designed to operate with multiple reference frequencies. During boot up the processor
samples PIO pins to determine the default reference frequency. If the USB transport is selected, the default reference
frequency will always be 32 MHz. If the UART transport is selected, the reference frequency setting will be set according
to the following table:
Application Software Memory Selection
The SiW3000 can support application (protocol stack) software execution from internal ROM and external FLASH mem-
ory. To run from internal ROM, D[9] and D[10] pins must be connected together as shown in the application circuit sec-
tion of this document. To run from external FLASH memory the FLASH must be connected as shown in the application
circuit diagram and contain valid application code. If an external memory does not have valid program data, the device
enters a download mode in which a valid program may be loaded into the external memory through a sequence of com-
mands over the HCI transport layer.
Value (PIO 2)
Description
0UART
1USB
PIO 1
USB_DPLS_PULLUP
Reference Frequency Selection
1Don't Care
Reference frequency per NVM system configu-
ration setting, or if NVM is not set, defaults to
32 MHz.
0
0
13 MHz
0
1
26 MHz
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