CLC2011 datasheet(10/17 Pages) EXAR

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exar.com/CLC2011

Rev 1D

CLC2011, CLC4011

In order to determine PD, the power dissipated in the load

needs to be subtracted from the total power delivered by the

supplies.

PD = Psupply - Pload

Supply power is calculated by the standard power equation.

Psupply = Vsupply × IRMSsupply

Vsupply = VS+ - VS-

Power delivered to a purely resistive load is:

Pload = ((Vload)RMS2)/Rloadeff

The effective load resistor (Rloadeff) will need to include

the effect of the feedback network. For instance, Rloadeff in

Figure 3 would be calculated as:

RL || (Rf + Rg)

These measurements are basic and are relatively easy to

perform with standard lab equipment. For design purposes

however, prior knowledge of actual signal levels and load

impedance is needed to determine the dissipated power.

Here, PD can be found from

PD = PQuiescent + PDynamic - Pload

Quiescent power can be derived from the specified IS values

along with known supply voltage, Vsupply. Load power can

be calculated as above with the desired signal amplitudes

using:

(Vload)RMS = Vpeak / √2

( Iload)RMS = ( Vload)RMS / Rloadeff

The dynamic power is focused primarily within the output

stage driving the load. This value can be calculated as:

PDynamic = (VS+ - Vload)RMS × ( Iload)RMS

Assuming the load is referenced in the middle of the power

rails or Vsupply/2.

The CLC2011 is short circuit protected. However, this may

not guarantee that the maximum junction temperature

(+150°C) is not exceeded under all conditions. Figure 5

shows the maximum safe power dissipation in the package

vs. the ambient temperature for the packages available.

0.5

1.5

2.5

-40

-20

100

120

Ambient Temperature (°C)

MSOP-8

SOIC-8

TSSOP-14

SOIC-14

Figure 5. Maximum Power Derating

Input Common Mode Voltage

The common mode input range extends to 250mV below

ground and to 250mV above Vs, in single supply operation.

Exceeding these values will not cause phase reversal.

However, if the input voltage exceeds the rails by more

than 0.5V, the input ESD devices will begin to conduct. The

output will stay at the rail during this overdrive condition. If

the absolute maximum input voltage (700mV beyond either

rail) is exceeded, externally limit the input current to ±5mA

as shown in Figure 6.

Input

Output

10k

Figure 6. Circuit for Input Current Protection

Driving Capacitive Loads

Increased phase delay at the output due to capacitive loading

can cause ringing, peaking in the frequency response, and

possible unstable behavior. Use a series resistance, RS,

between the amplifier and the load to help improve stability

and settling performance. Refer to Figure 7.

Input

Output

Figure 7. Addition of RS for Driving Capacitive Loads

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