Preliminary W49V002A

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"1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot

block from "0" to "1", is needed before programming.

The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte

Programming). The device will internally enter the program operation immediately after the byte-program

command is entered. The internal program timer will automatically time-out (100

is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect

end of program cycle.

Boot Block Operation and Hardware Protection at Initial- #TBL & #WP

There are two alternatives to set the boot block. One is software command sequences method; the other

is hardware method. 16K-byte in the top location of this device can be locked as boot block, which can

be used to store boot codes. It is located in the last 16K bytes of the memory with the address range

from 3C000(hex) to 3FFFF(hex).

Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is

set, the data for the designated block cannot be erased or programmed (programming lockout), other

memory locations can be changed by the regular programming method.

Besides the software method, there is a hardware method to protect the top boot block and other

sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block

will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will

override the software method setting. That is, if #TBL is at low state, then top boot block cannot be

programmed/erased no matter how the software boot block lock setting.

Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The

enable of this pin will override the #TBL setting. That is, the top boot block cannot be

programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.

Hardware Data Protection

The integrity of the data stored in the W49V002A is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.

typical.

(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents

inadvertent writes during power-up or power-down periods.

mS before any write (erase/program) operation.

The W49V002A includes a data polling feature to indicate the end of a program or erase cycle. When

has been completed it becomes logical "1" or true data.

In addition to data polling, the W49V002A provides another method for determining the end of a program

alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's

will stop. The device is then ready for the next operation.