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TM4EP72CPN Datasheet(PDF) 13 Page - Texas Instruments

Part # TM4EP72CPN
Description  EXTENDED-DATA-OUT DYNAMIC RAM MODULES
PDF  22 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TM4EP72CPN Datasheet(HTML) 13 Page - Texas Instruments

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TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
13
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ac timing requirements (see Note 3)
’4EP64xxN-50
’4EP72xxN-50
’4EP64xxN-60
’4EP72xxN-60
’4EP64xxN-70
’4EP72xxN-70
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tRC
Cycle time, random read or write
84
104
124
ns
tRWC
Cycle time, read-write
111
135
160
ns
tRASP
Pulse duration, RASx active, fast-page mode (see Note 6)
50
100 000
60
100 000
70
100 000
ns
tRAS
Pulse duration, RASx active, non-page mode (see Note 6)
50
10 000
60
10 000
70
10 000
ns
tRP
Pulse duration, RASx precharge
30
40
50
ns
tWP
Pulse duration, write command
8
10
10
ns
tASC
Setup time, column address
0
0
0
ns
tASR
Setup time, row address
0
0
0
ns
tDS
Setup time, data in (see Note 7)
0
0
0
ns
tRCS
Setup time, read command
0
0
0
ns
tCWL
Setup time, write command before CASx precharge
8
10
12
ns
tRWL
Setup time, write command before RASx precharge
8
10
12
ns
tWCS
Setup time, write command before CASx active
(early-write only)
0
0
0
ns
tWRP
Setup time, WEx high before RASx low (CBR refresh only)
10
10
10
ns
tWTS
Setup time, WEx low before RASx low (test mode only)
10
10
10
ns
tCSR
Setup time, CASx referenced to RASx ( CBR refresh only )
5
5
5
ns
tCAH
Hold time, column address
8
10
12
ns
tDH
Hold time, data in (see Note 7)
8
10
12
ns
tRAH
Hold time, row address
8
10
10
ns
tRCH
Hold time, read command referenced to CASx (see Note 8)
0
0
0
ns
tRRH
Hold time, read command referenced to RASx (see Note 8)
0
0
0
ns
tWCH
Hold time, write command during CASx active ( early-write only )
8
10
12
ns
tROH
Hold time, RASx referenced to OEx
10
10
10
ns
tWRH
Hold time, WEx high after RASx low (CBR refresh)
10
10
10
ns
tWTH
Hold time, WEx low after RASx low (test mode only)
10
10
10
ns
tCHR
Hold time, CASx referenced to RASx ( CBR refresh only )
10
10
10
ns
tOEH
Hold time, OEx command
13
15
18
ns
tCHS
Hold time, CASx referenced to RASx ( self-refresh only)
– 50
– 50
– 50
ns
tRHCP
Hold time, RASx active from CASx precharge
28
35
40
ns
tAWD
Delay time, column address to write command ( read-write only )
42
49
57
ns
tCPW
Delay time, WEx low after CASx precharge (read-write only)
45
54
62
ns
tCRP
Delay time, CASx precharge to RASx
5
5
5
ns
tCWD
Delay time, CASx to write command ( read-write only )
30
34
40
ns
tOED
Delay time, OEx to data in
13
15
18
ns
tRAD
Delay time, RASx to column address (see Note 9)
10
25
12
30
12
35
ns
tRAL
Delay time, column address to RASx precharge
25
30
35
ns
tCAL
Delay time, column address to CASx precharge
18
20
25
ns
NOTES:
3. With ac parameters, it is assumed that tT = 2 ns.
6. In a read-write cycle, tRWD and tRWL must be observed.
7. Referenced to the later of CASx or WEx in write operations
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. The maximum value is specified only to ensure access time.



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