Pin Description

Signal Ground (3, 19): Each input has its own independent

ground, GND1 and GND2.

Signal Input (4, 20): There are 2 independent signal inputs,

IN1 and IN2.

Signal Output (2, 17): There are 2 independent signal out-

puts, OUT1 and OUT2.

Voltage Supply (13, 15): Positive voltage supply pins, V

DD1

and V

Voltage Supply (7, 18): Negative voltage supply pins, V

SS1

and V

tion.

AC Ground (1, 5, 6, 14, 16): These five pins are not physi-

cally connected to the die in any way (i.e., No bondwires).

These pins must be AC grounded to prevent signal coupling

between any of the pins nearby. Pin 14 should be connected

to pins 13 and 15 for ease of wiring and the best isolation, as

an example.

Logic Ground (8): Digital signal ground for the interface

lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.

Clock (9): The clock input accepts a TTL or CMOS level sig-

nal. The clock input is used to load data into the internal shift

register on the rising edge of the input clock waveform.

Load/Shift (10): The load/shift input accepts a TTL or

CMOS level signal. This is the enable pin of the device, al-

lowing data to be clocked in while this input is low (0V).

Data-In (11): The data-in input accepts a TTL or CMOS level

signal. This pin is used to accept serial data from a micro-

controller that will be latched and decoded to change a chan-

nel’s attenuation level.

Data-Out (12): This pin is used in daisy-chain mode where

more than one µPot is controlled via the same data line. As

the data is clocked into the chain from the µC, the preceding

data in the shift register is shifted out the DATA-OUT pin to

the next µPot in the chain or to ground if it is the last µPot in

the chain. The LOAD/SHIFT line goes high once all of the

new data has been shifted into each of its respective regis-

ters.

Connection Diagram

DS011978-3

FIGURE 2. Timing Diagram

DS011978-4

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