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DSC400

Page 3

DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator

Operational Description

The DSC400 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it

does not require an external crystal to operate; it relies on the integrated MEMS resonator that

interfaces with internal PLLs. This technology enhances performance and reliability by allowing

tighter frequency stability over a far wider temperature range. In addition, the higher resistance to

shock and vibration decreases the aging rate to allow for much improved product life in the system.

Inputs

There are 4 input signals in the device. Each has an internal (40kΩ) pull up to default the selection

to a high (1). Inputs can be controlled through hardware strapping method with a resistor to

ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs

In case more than one frequency set is desired, FSB1 and FSB2 are used for independently

selecting one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3)

and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in table 2.

If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to

disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.

Table 1: Output Enable (OE) Selection Table

OE1 OE2 Bank1 (CLK0 & CLK3) Bank2 (CLK1 & CLK2)

0

0

Hi-Z

Hi-Z

0

1

Hi-Z

Running

1

0

Running

Hi-Z

1

1

Running

Running

Outputs

The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to

allow for optimized noise isolation between the two banks. Each bank provides two synchronous

outputs generated by a common PLL:

 Bank1 is composed of outputs CLK0 and CLK3

 Bank2 is composed of outputs CLK1 and CLK2

Each output maybe pre-configured independently to be one of the following formats: LVCMOS,

LVDS, LVPECL or HCSL. In case the output is configured to be the single ended LVCMOS, the

frequency is generated on the true output (CLKx+) and the complement output (CLKx-) is shut off

in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential outputs and from

2.3MHz to 170MHz on LVCMOS outputs.

Power

VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different

supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each VDD pin should

have a 0.1µF capacitor to filter high frequency noise. VSS is common to the entire device.