GL603USB datasheet(14/41 Pages) ETC

14 / 41 page

09/22/00

GL603USB/GL603USB-A/GL603USB-B

Revision 1.4

15h

FFCNT1

Byte count buffer for endpoint 1

16h

FFCTL

FIFO control register

17h

FFDAT0

Endpoint 0 FIFO port

18h

FFDAT1

Endpoint 1 FIFO port

19h

EP0RXST

Endpoint 0 receiving status register

Table 4 -1 USB Function Register Summary

DEVCTL (Address 10h, Device control register)

R/W

[1]

R/W

TXSE0

EP0STL

EP1STL

WAKE

WKDIS

PWRDN

TXSE0: Set and clear transmitting SE0 bit

1: Set transmitting SE0

0: Clear transmitting SE0

EP0STL: Endpoint 0 stall bit. This bit will be cleared automatically by hardware when SETUP packet is

received

1: Endpoint 0 will respond with a STALL to a valid transaction except SETUP

0: Endpoint 0 will not respond with a STALL to a valid transaction

EP1STL: Endpoint 1 stall bit

1: Endpoint 1 will respond with a STALL to a valid transaction

0: Endpoint 1 will not respond with a STALL to a valid transaction

WAKE: Wake-up bit

1: Set this bit to wake up host controller by placing USB bus into K state

0: Clear this bit to force USB bus leave K state

WKDIS: Wake-up disable bit. The WAKE bit has no effect if WKDIS bit is set to 1.

1: Disable remote wake-up capability

0: Enable remote wake-up capability

PWRDN: Power-down mode bit. Writing 1 to this bit will enter power-down mode

If USB suspend is detected, firmware can set this bit to enter power-down mode. In power-down

mode, crystal/resonator will stop. The PWRDN bit will be cleared automatically by hardware and

crystal/resonator will restart when the internal RC timer timeout (about 300ms for mask, 500ms

for OTP). Firmware should check buttons and photo position encoders of the mouse. If mouse

status is not changed, Firmware should set the PWRDN bit to enter power down mode again.

Power consumption in suspend mode depends on how much time the firmware checking mouse

status changed. Hardware will also clear PWRDN bit automatically when USB D+ or D- is

toggled.

0: Normal mode, not power-down

Value on POR: “1 - 0 - 0 0 0 0”

[2]

Note 1: “R/W” means readable and writable bit. All reserved fields should not be changed by firmware.

Note 2: “-“ means unimplemented read as 0

MODSEL (Address 11h, Mode select register)

R/W

USBPS2

USBPS2: USB or PS/2 mode selector bit

1: USB mode, enable SIE

0: PS/2 mode, disable SIE

Value on POR: “- - - 0 - - - -”

EVTFLG (Address 12h, Event flag register)

R/W1C

[1]

R/W1C

RESUME

SUSPD

EP1TX

EP0TX

EP0RX

RESUME: Global resume bit

1: Global resume (USB D+/D- toggle) was detected

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