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TLV172IDBVT Datasheet(PDF) 21 Page - Texas Instruments |
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TLV172IDBVT Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 42 page ![]() 1 10 100 1000 0.01 0.1 1 10 100 1000 C LOAD (nF) 60°Phase Margin 45°Phase Margin C041 0 AOL 1/ 20 40 60 80 10 100 1k 10k 100k 1M 100 120 10M 100M Frequency (Hz) 20 dB ROC dec 40 dB 1 dec z ISO LOAD 1 f 2 R C Œ u u u p ISO o LOAD 1 f 2 R R C Œ u u u 21 TLV172, TLV2172, TLV4172 www.ti.com SBOS784 – NOVEMBER 2016 Product Folder Links: TLV172 TLV2172 TLV4172 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Typical Application (continued) Figure 30. Unity-Gain Amplifier With RISO Compensation ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a measurement of overshoot percentage and ac gain peaking of the circuit using a function generator, oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3 shows the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For more details on this design and other alternative devices that can be used in place of the TLV172, see the Capacitive Load Drive Solution Using an Isolation Resistor precision design. Table 3. Phase Margin versus Overshoot and AC Gain Peaking PHASE MARGIN OVERSHOOT AC GAIN PEAKING 45° 23.3% 2.35 dB 60° 8.8% 0.28 dB 9.2.3 Application Curve Using the described methodology, the values of RISO that yield phase margins of 45º and 60º for various capacitive loads were determined. The results are shown in Figure 31. Figure 31. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin |
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