Document Number: 002-14786 Rev. *E

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CYW20704

4. Microprocessor Unit

4.1 Overview

The CYW20704 microprocessor unit runs software from the Link Control (LC) layer up to the Host Controller Interface (HCI). The

microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The

microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad,

and patch RAM code.

The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations,

including automatic host transport selection from UART and USB transports with or without external NVRAM. At power-up, the lower

layer protocol stack is executed from the internal ROM.

External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches

can be downloaded from the host to the device through the SPI interface or UART and USB transports, or using external NVRAM.

The device can also support the integration of user applications and profiles using an external serial flash memory.

4.2 NVRAM Configuration Data and Storage

4.2.1 Serial Interface

The CYW20704 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB

slave interface, transmit and receive FIFOs, and the SPI core PHY logic. Data is transferred to and from the module by the system

CPU. DMA operation is not supported.

4.3 EEPROM

The CYW20704 includes a Cypress Serial Control (BSC) master interface. The BSC interface supports low-speed and fast mode

or slave devices are not supported. The CYW20704 provides 400 kHz, full speed clock support.

The BSC interface is programmed by the CPU to generate the following BSC transfer types on the bus:

NVRAM may contain configuration information about the customer application, including the following:

4.4 External Reset

The CYW20704 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action

can also be driven by an external reset signal, which can be used to externally control the device, forcing it into a power-on reset

state. The RST_N signal is an active-low signal, which is an input to the CYW20704 chip. The CYW20704 does not require an exter-

nal pull-up resistor on the RST_N input.