Technical Data

3-Pin Microprocessor Reset Circuits

Data Sheet N1589 Rev. -

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SSR809N

SSR809P/SSR810P

Pin Descriptions

GND Pin

: Ground.

RESET

———————

Pin (SSR809P) : Active low output pin. RESET

———————

Output remains low while Vcc is below the reset

threshold.

RESET Pin (SSR810P) : Active high output pin. RESET output remains high while Vcc is below the reset

threshold.

Vcc Pin

: Supply voltage.

Detail Descriptions of Technical Terms

RESET OUTPUT

μP will be activated at a valid reset state. These μP supervisory circuits assert reset to prevent code

execution errors during power-up, power-down, or brownout conditions.

RESET

———————

is guaranteed to be a logic low for V

TH

>VCC>0.9V. Once VCC exceeds the reset threshold, an

internal timer keeps RESET

———————

low for the reset timeout period; after this interval, RESET

———————

goes high.

If a brownout condition occurs (VCC drops below the reset threshold), RESET

———————

goes low. Any time VCC goes

below the reset threshold, the internal timer resets to zero, and RESET

———————

goes low. The internal timer is

activated after VCC returns above the reset threshold, and RESET

———————

remains low for the reset timeout period.

BENEFITS OF HIGHLY ACCURATE RESET THRESHOLD

SSR809P/SSR810P with specified voltage as 5V±10% or 3V±10% are ideal for systems using a 5V±5% or

3V±5% power supply. The reset is guaranteed to assert after the power supply falls out of regulation, but

before power drops below the minimum specified operating voltage range of the system ICs. The pre-trimmed

thresholds are reducing the range over which an undesirable reset may occur.