OPA690 datasheet(19/23 Pages) TI

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OPA691

SBOS226A

www.ti.com

input voltage at the inputs of the OPA237 (this is a low-cost,

precision voltage feedback op amp with 1.5MHz gain band-

width product). If these two don’t agree (due to DC offsets

introduced by the OPA691), the OPA237 sums in a correc-

tion current through the 2.86k

Ω inverting summing path.

Several design considerations will allow this circuit to be

optimized. First, the feedback to the OPA237’s noninverting

input must be precisely matched to the high-speed signal

gain. Making the 2k

Ω resistor to ground an adjustable resis-

tor would allow the low and high frequency gains to

be precisely matched. Secondly, the crossover frequency

region where the OPA237 passes control to the OPA691

must occur with exceptional phase linearity. These two

issues reduce to designing for pole/zero cancellation in the

overall transfer function. Using the 2.86k

Ω resistor will nomi-

nally satisfy this requirement for the circuit in Figure 11.

Perfect cancellation over process and temperature is not

possible. This initial resistor setting and precise gain match-

ing, however, will minimize long-term pulse settling tails.

When disabled, the output and input nodes go to a high

impedance state. If the OPA691 is operating in a gain of +1,

this will show a very high impedance (4pF || 1M

Ω) at the

output and exceptional signal isolation. If operating at a

gain greater than +1, the total feedback network resistance

(RF + RG) will appear as the impedance looking back into the

output, but the circuit will still show very high forward and

reverse isolation. If configured as an inverting amplifier, the

input and output will be connected through the feedback

network resistance (RF + RG) giving relatively poor input-to-

output isolation.

One key parameter in disable operation is the output glitch

when switching in and out of the disabled mode. Figure 13

shows these glitches for the circuit of Figure 1 with the input

signal set to 0V. The glitch waveform at the output pin is

plotted along with the DIS pin voltage.

The transition edge rate (dV/dT) of the DIS control line will

influence this glitch. For the plot of Figure 12, the edge rate

was reduced until no further reduction in glitch amplitude was

observed. This approximately 1V/ns maximum slew rate may

be achieved by adding a simple RC filter into the V

DIS pin

from a higher speed logic line. If extremely fast transition

logic is used, a 2k

Ω series resistor between the logic gate

and the DIS input pin will provide adequate bandlimiting

using just the parasitic input capacitance on the DIS pin

while still ensuring an adequate logic level swing.

FIGURE 11. Wideband, DC Connected Composite Circuit.

FIGURE 12. Simplified Disable Control Circuit.

DISABLE OPERATION

The OPA691 provides an optional disable feature that may

be used to reduce system power. If the DIS control pin is left

unconnected, the OPA691 will operate normally. To disable,

the control pin must be asserted LOW. Figure 12 shows a

simplified internal circuit for the disable control feature.

In normal operation, base current to Q1 is provided through

the 110k

Ω resistor while the emitter current through the 15kΩ

resistor sets up a voltage drop that is inadequate to turn on

the two diodes in Q1’s emitter. As V

DIS is pulled LOW,

additional current is pulled through the 15k

Ω resistor eventu-

ally turning on these two diodes (

≈ 75µA). At this point, any

further current pulled out of V

DIS goes through those diodes

holding the emitter-base voltage of Q1 at approximately 0V.

This shuts off the collector current out of Q1, turning the

amplifier off. The supply current in the disable mode are only

those required to operate the circuit of Figure 12. Additional

circuitry ensures that turn-on time occurs faster than turn-off

time (make-before-break).

OPA691

180

Ω

2.86k

Ω

DIS

+5V

–5V

Power supply

de-coupling not shown

OPA237

–5V

+5V

18k

Ω

1.8k

Ω

FIGURE 13. Disable/Enable Glitch.

25k

Ω

110k

Ω

15k

Ω

Control

–V

DIS

–10

–20

–30

Time (20ns/div)

6.0

4.0

2.0

DIS

Output Voltage

(0V Input)

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