PC87373 datasheet(50/174 Pages) NSC

50 / 174 page

3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.8.3

FDC Configuration Register

This register is reset to 24h.

Power Well: VDD3

Location:

Indexes F0h and F8h

Type:

R/W

Bit

76543210

Name

Reserved

TDR

Mode

DENSEL

Polarity

Control

FDC 2Mbps

Enable

Write

Protect

PC-AT or

PS/2 Drive

Mode Select

Reserved

TRI-STATE

Control

Reset

00100100

Bit

Description

Reserved.

TDR Register Mode.

0: PC-AT-Compatible Drive mode; i.e., bits 7-2 of the TDR are ‘111111’ (default)

1: Enhanced Drive mode

DENSEL Polarity Control.

0: Active low for 500 Kbps or 1 or 2 Mbps data rates

1: Active high for 500 Kbps or 1 or 2 Mbps data rates (default)

FDC 2Mbps Enable. This bit is set only when a 2 Mbps drive is used.

0: 2 Mbps disabled and the FDC clock is 24 MHz (default)

1: 2 Mbps enabled and the FDC clock is 48 MHz

Write Protect. This bit enables forcing of write protect functionality by software. When set, writes to the floppy

disk drive are disabled. This effect is identical to an active WP signal.

0: Write protected according to WP signal (default)

1: Write protected regardless of value of WP signal

PC-AT or PS/2 Drive Mode Select.

0: PS/2 Drive mode

1: PC-AT Drive mode (default)

Reserved.

TRI-STATE Control. When this bit is set to 1 and the logical device is inactive, the logical device output pins are

in TRI-STATE (see Section 3.3.2 on page 41).

0: Normal outputs (default)

1: TRI-STATE outputs when the logical device is inactive

PC87373 Datasheet(PDF) 50 Page - National Semiconductor (TI)

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