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RT9241CS Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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RT9241CS Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
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10 / 13 page ![]() RT9241 Preliminary www.richtek-ic.com.tw DS9241-00 November 2001 10 S 5 V V V T IN O IN OFF µ × − = The sensing circuit gets IX = by local feedback. RSP = RSN to cancel the voltage drop caused by GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off (See Fig.2). Therefore, , , , for operating frequency = 200kHz Fig. 2 Inductor Current and PWM Signal Droop Tuning The S/H current signals from power channels are injected to ADJ pin to create droop voltage. The DAC output voltage decreases by VADJ to form the VCORE load droop(see Fig.3). Fig. 3 Droop Tune Circuit Protection and SS function For OVP, the RT9241 detects the VCORE by VSEN pin. Eliminate the parasitic delay and noise influence on the PCB path for fast and accurate detection. The trip point of OVP is 120% of normal output level. The PWM outputs are pulled low to turn on the low side MOSFET and turn off the high side MOSFET of the synchronous rectifier at OVP. The OVP latch can only be reset by VDD or DVD restart power on reset sequence. The PGOOD detection trip point of VCORE is ±8% out of the normal level. The PGOOD open drain output pulls low when VOCRE exceeds the range. Soft start circuit generates a ramp voltage by charging external capacitor with 10uA current after IC POR acts. The PWM pulse width and VCORE are clamped by the rising ramp to reduce the in-rush current and protect the power devices. Over current protection trip point is set by the resistor RIMAX connected to IMAX pin. OCP is triggered if one channel S/H current signal IX> . Controller forces PWM output latched at high impedance to turn off both high and low side MOSFET in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 10 µA current after it is less than 90% VDD. The converter restarts after SS pin voltage < 0.2V. Three times of OCP disable the converter and only release the latch by POR acts (see Fig.4). Fig. 4 SP S L R R I × SP S ) H / S ( L ) H / S ( X R R I I × = 2 T L V I I OFF O ) AVG ( L ) H / S ( L × − = SP S IN O IN O ) AVG ( L ) H / S ( X R R L 2 S 5 V V V V I I × µ × − − − = ∑ × = X ADJ ADJ I 3 2 R V IMAX R 6 . 0 2 3 × _ EA ∑ ∑ I X FB COMP VDAC - VADJ + _ VDAC VADJ ADJ RADJ 2/3 IX1 2/3 IX2 2/3 IX3 2/3 IX4 0A 0V 2V 4V T0T1 T2 T3T4 TIME COUNT = 1 COUNT = 2 COUNT = 3 OVERLOAD APPLIED SS VCORE IL Falling Slope = V O /L I L I L (S/H) I L (AVG) PWM Signal & High Side MOSFET Gate Signal Low Side MOSFET Gate Signal Inductor Current |
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