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CS5301

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3. For resistive current sensing choose L and RS to

provide a steady state ramp greater than 25 mV.

L RS + (VIN * VOUT)

VOUT VIN

25 mV

Again the ratio of L and RL is fixed and the values of

L and RS will be a compromise.

4. Calculate the high frequency output impedance

(ConverterZ) of the converter during transients. This

is the impedance of the Output filter ESR in parallel

with the power stage output impedance (PwrstgZ)

and will indicate how far from the original level

(

∆VR) the output voltage will typically recover to

within one switching cycle. For a good transient

response

∆VR should be less than the peak output

voltage overshoot or undershoot.

DVR + ConverterZ

IOUT

ConverterZ

PwrstgZ

ESR

PwrstgZ

) ESR

where:

PwrstgZ

+ RS

CSA Gain 3

Multiply the converterZ by the output current step

size to calculate where the output voltage should

recover to within the first switching cycle after a

transient. If the ConverterZ is higher than the value

required to recover to where the adaptive positioning

is set the remainder of the recovery will be controlled

by the error amp compensation and will typically

recover in 10–20

µs.

DVR + DIOUT

ConverterZ

Make sure that

∆VR is less than the expected peak

transient for a good transient response.

5. Adjust L and RL or RS as required to meet the best

combination of transient response, steady state output

voltage ripple and pulse width jitter.

Current Limit

When the sum of the Current Sense amplifiers (VITOTAL)

exceeds the voltage on the ILIM pin the part will enter hiccup

mode. For inductive sensing the ILIM pin voltage should be

set based on the inductor resistance (or current sense

resistor) at max temperature and max current. To set the level

of the ILIM pin:

VILIM +

where:

R is RL or RS;

IOUT(LIM) is the current limit threshold.

For the overcurrent to work properly the inductor

time constant (L/R) should be

≤ the Current sense RC.

If the RC is too fast, during step loads the current

waveform will appear larger than it is (typically for a

few hundred

µs) and may trip the current limit at a

level lower than the DC limit.

Adaptive Positioning

7. To set the amount of voltage positioning above the

DAC setting at no load connect a resistor (RVFB)

between the output voltage and the VFB pin. Choose

RVFB as;

RVFB + NL Position VFB Bias Current

See Figure 4 for VFB Bias Current.

8. To set the difference in output voltage between no

load and full load, connect a resistor (RVDRP)

between the VDRP and VFB pins. RVDRP can be

calculated in two steps. First calculate the difference

between the VDRP and VFB pin at full load. (The VFB

voltage should be the same as the DAC voltage during

closed loop operation.) Then choose the RVDRP to

source enough current across RVFB for the desired

change in output voltage.

DVVDRP + R

IOUT

CS to VDRP Gain

where:

R = RL or RS for one phase;

IOUT is the full load output current.

RVDRP + DVVDRP

RV(FB) DVOUT

DESIGN EXAMPLE

Choose the component values for lossless current sensing,

adaptive positioning and current limit for a 250 kHz, 1.55 V,

60 A converter. The VID code is set to 1.6 V. Adaptive

positioning is set for 100 mV above DACOUT (or 25 mV

below VID) at no load and 75 mV below the no load position

with a 60 A load. The peak output voltage transient should

be less than 100 mV during a 60 A step current. The

overcurrent limit is nominally 75 A.

Current Sensing, Power Stage and

Output Filter Components

1. Assume 1.5 m

Ω of output filter ESR.

2. Choose C

+ 0.01 mF

+ (VIN * VOUT)

VOUT VIN

25 mV

+ (12 * 1.55)

1.55 12

250 k

0.01

25 mV

+ 21.5 kW å Choose 20 kW

L RL + R

+ 20 kW

0.01

mF + 200 ms

Choose RL + 2.0 mW

+ RL

+ 2.0 mW

200

ms + 400 nH

3. n/a

4. PwrstgZ

+ RL

CSA Gain 3

+ 2.0 mW

4.2 3.0

+ 2.8 mW

ConverterZ

PwrstgZ

ESR

PwrstgZ

) ESR

+ 2.8 mW

1.5 m

2.8 m

W ) 1.5 mW

^ 1.0 mW

DVR + ConverterZ

IOUT

+ 1.0 mW

60 A

+ 60 mV

5. n/a

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