PMC-1981271 (R4)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR IT’S CUSTOMERS’ INTERNAL USE

 2001 PMC-Sierra, Inc.

PM5313

PMC-Sierra,Inc.

SONET/SDH Payload Extractor/Aligner for 622 Mbit/s Interfaces

SPECTRA-622

FEATURES

The SPECTRA-622 chip offers the

following features:

• Monolithic SONET/SDH

Payload-Extractor/Aligner for use in

STS-12 (STM-4/AU3 or STM-4/AU4) or

STM-12c (STM-4/AU4-4c) interface

applications that operate at serial

interface speeds up to 622.08 Mbit/s.

• Provides integrated clock recovery and

clock synthesis to allow a direct interface

to optical modules.

• Complies with Bellcore GR-253-CORE

jitter tolerance and intrinsic jitter criteria.

• Provides control circuitry required to

comply with WAN clocking requirements

for wander, holdover, and long term

stability.

• Provides termination for SONET Section

and Line, and SDH Regenerator Section

and Multiplexer Section

transport-overhead. Also provides

termination for Path overhead of twelve

STS-1 (STM-0/AU3) paths, four STS-3/

3c (STM-1/AU3/AU4) paths, or a single

STS-12c (STM-4/AU4-4c) path.

• Maps twelve STS-1 (STM-0/AU3)

payloads, four STS-3/3c (STM-1/AU3/

AU4) payloads, or a single STS-12c

(STM-4/AU4-4c) payload to system

timing references. This accommodates

plesiochronous timing offsets between

the references.

• Maps twelve DS3 bit-streams into an

STS-12 (STM-4/AU3) frame.

• Configurable on an STS-1 basis to

support a mix of traffic from the DS-3 and

Telecom interfaces.

• Provides a Time-Slot Interchange (TSI)

function on the Telecom Add and Drop

buses for grooming twelve STS-1

(STM-0/AU3) paths or four STS-3/3c

(STM-1/AU3/AU4) paths.

• Supports line loopback and diagnostic

loopback.

• Supports OC-48 (STM-16) applications

with byte interfaces for connection to

an OC-48 front-end device.

pseudo-random bit-sequence (PRBS)

generation and monitoring.

• Provides a standard JTAG test-port for

boundary scan board-test purposes.

• Provides a generic 8-bit

microprocessor bus-interface.

• Low-power 3.3V CMOS with TTL

compatible inputs and CMOS/TTL

digital outputs. PECL inputs and

outputs are 3.3V and 5V compatible.

• Available in a 520-pin SBGA package.

• Supports industrial temperature-range

(-40°C to 85°C) operation.

Drop Bus PRBS

Generator/

Monitor

Rx Telecom

Aligner

Rx Path O/H

Processor

DS3 Mapper

Add Side

Tx Transport O/H

Controller

DS3 Mapper

Drop Side

Receive Path Processing Slice x12

Serial

Control Port

Microprocessor Interface

JTAG Test

Access Port

Rx Transport O/H

Controller

Path Trace Buffer

Tx Path O/H

Processor

Transmit Path Processing Slice x12

Rx Ring

Control Port

Tx Ring

Control Port

TDP

RRCLK+/-

RXD+/-

REFCLK+/-

PECLV

TD[7:0]

TFPI

TPL

TC1J1V1/TFPO

TDCK

TDREF/ TDREF1

TXD+/-

SD

C0, C1

PICLK

PIN[7:0]

FPIN

OOF

ATP[1:0]

PREFEN

PECLREF

DS3TICLK [12:1]

AC1J1V1[4:1]/

AFP[4:1]

APL[4:1]

AD[31:0]

ADP[4:1]

DCK

DC1J1V1[4:1]

DPL[4:1]

DD[31:0]

DDP[4:1]

DFP

DS3TDAT [12:1]

DS3RDAT [12:1]

DS3ROCLK [12:1]

DS3RICLK

ACK

TCLK/PGMTCLK

/TFP

RCLK/PGMRCLK

/RFP

DPAIS

DMODE[1:0]

DPAISFP

DPAISCK

TPAIS

TPAISFP

TPAISCK

BLOCK

DIAGRAM