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9DML04 Datasheet(PDF) 2 Page - Integrated Device Technology |
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9DML04 Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 13 page ![]() 2:4 3.3V PCIE CLOCK MUX 2 REVISION A 06/06/16 9DML04 DATASHEET Pin Configuration Power Management Table Power Connections 24 23 22 21 20 19 DIF_INA 1 18 DIF2# DIF_INA# 2 17 DIF2 VDDR3.3 3 16 VDD3.3 VDDR3.3 4 15 GND DIF_INB 5 14 DIF1# DIF_INB# 6 13 DIF1 7 8 9 101112 24 VFQFPN, 4x4 mm, 0.5mm pitch ^ prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor 9DML04xx Connect ePad to GND True O/P Comp. O/P 0 Running Running Running 1 Running Low Low DIF_IN OEx# Pin DIFx VDD GND 324 47 16 15 DIF outputs Description Pin Number Input A receiver analog Input B receiver analog |
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