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EM6AB080WKB-5H Datasheet(PDF) 13 Page - Etron Technology, Inc.

Part # EM6AB080WKB-5H
Description  64M x 8 bit DDR Synchronous DRAM (SDRAM
PDF  62 Pages
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Manufacturer  ETRON [Etron Technology, Inc.]
Direct Link  http://www.etron.com
Logo ETRON - Etron Technology, Inc.

EM6AB080WKB-5H Datasheet(HTML) 13 Page - Etron Technology, Inc.

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EtronTech
EM6AB080
Etron Confidential
13
Rev.1.1
Dec. /2013
Table 17. Recommended A.C. Operating Conditions (VDD = 2.5V ± 0.2V, TA = 0~70 °C)
Symbol
Parameter
Min.
Max.
Unit
VIH (AC) Input High Voltage (AC)
VREF + 0.31
-
V
VIL (AC) Input Low Voltage (AC)
-
VREF – 0.31
V
VID (AC) Input Different Voltage, CK and CK inputs
0.7
VDDQ + 0.6
V
VIX (AC) Input Crossing Point Voltage, CK and CK inputs
0.5 x VDDQ-0.2
0.5 x VDDQ+0.2
V
Note:
1) Enables on-chip refresh and address counters.
2) Min(tCL, tCH) refers to ther smaller of the actual clock low time and actual clock high time as provided to the
device.
3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters
are not referenced to a specific voltage level, but specify when the device output is no longer driving(HZ),
or begins driving(LZ).
4) The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or
before this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate
specifications of the device. When no writes were previously in progress on the bus, DQS will be
transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or
transitioning from HIGH to LOW at this time, depending on tDQSS.
5) The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
6) For command/address and CK & CK slew rate ≧ 1.0V/ns.
7) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
8) Power-up sequence is described in Note 10
9) A.C. Test Conditions
Table 18. SSTL _2 Interface
Reference Level of Output Signals (VREF)
0.5 x VDDQ
Output Load
Reference to the Test Load
Input Signal Levels
VREF+0.31 V / VREF-0.31 V
Input Signals Slew Rate
1 V/ns
Reference Level of Input Signals
0.5 x VDDQ



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