PM7367

PMC-Sierra,Inc.

32 link, 32 Channel Data Link Manager with PCI Interface

FREEDM-32P32

PMC-2000358 (r2)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

© Copyright PMC-Sierra, Inc. 2001

FEATURES

• High density HDLC controller ideal for

Internet access, Frame Relay, and

Multiservice Switch equipment

supporting rates ranging from 56 Kbit/s

to 52 Mbit/s.

• Supports 32 full-duplex and

independently-timed links.

• Supports 32 full-duplex HDLC or

transparent channels.

• Supports a TimePipe

 architecture

that enables any physical link to be

flexibly mapped to one or more HDLC

channels.

• Provides 8 KB partial packet FIFO in

each transmit and receive direction to

compensate for PCI bus latency during

data transfers. The 8 KB partial packet

FIFO is arranged as 512 blocks of 16-

byte buffers.

• The TimePipe architecture supports

programmable assignment of partial

packet buffers to HDLC channels.

• Two physical links can support up to

52 Mbit/s; the remaining 30 physical

links can individually support up to

10 Mbit/s.

• Supports a mix of channelized and

unchannelized links.

• The maximum aggregate clock rate is

64 MHz. When the device is interfaced

to two T3 or HSSI links, the maximum

aggregate clock rate is 104 MHz.

• For channelized operation, the channel

assignment supports up to 24 timeslots

for a T1 link and 31 timeslots for an E1

link. Timeslots assigned to a common

HDLC channel can be noncontiguous.

• Performs flag delineation, bit de-

stuffing, CRC verification using either

CRC-32 or CRC-CCITT algorithm, and

length checking on receive HDLC

channels.

• Performs flag insertion, bit stuffing, and

FCS calculation using either CRC-32

or CRC-CCITT algorithm and length

checking on transmit HDLC channels.

• On the system side, provides a

33 MHz, 32-bit PCI 2.1 compatible bus

interface.

• Implements efficient transmit and

receive DMA controllers to support

burst data transfers between partial

packet FIFO and packet memory.

• Supports scatter-gather capabilities

whereby a packet can span multiple

buffers.

• Supports line-side loopback on a per-

link basis and system-side loopback on

a per-HDLC channel basis.

• Software-compatible with the PM7364

FREEDM-32

.

• Provides a standard 5-signal P1149.1

JTAG test port for boundary scan test

board purposes.

• Implemented in low power 3.3 V

CMOS technology with 5 V-tolerant

inputs.

• Packaged in a 272-pin Plastic Ball Grid

Array (PBGA) package.

APPLICATIONS

• Ideal for applications requiring HDLC,

PPP, and transparent protocol

processing for physical links, such as

T1, E1, T3, E3, xDSL, and HSSI.

• Frame-based Interfaces for Internet

Access and Multiservice Switch

equipment.

• FUNI or Frame Relay service

interworking interfaces for ATM

switches and multiplexers.

BLOCK DIAGRAM

PCIINTB

PCICLK

PCICLKO

SYSCLK

PERRB

SERRB

REQB

GNTB

STOPB

DEVSELB

IDSEL

LOCKB

JTAG Port

GPIC

PCI

Controller

RMAC

Receive

DMA

Controller

PMON

Performance Monitor

TimePipe Architecture

RHDL

Receive HDLC

Processor/

Partial Packet Buffer

THDL

Transmit HDLC

Processor/

Partial Packet Buffer

TCAS

Transmit

Channel Assigner

RCAS

Receive

Channel Assigner

TMAC

Transmit

DMA

Controller

PAR

FRAMEB

TRDYB

IRDYB

AD[31:0]

C/BEB[3:0]

TD[31:0]

TCLK[31:0]

RCLK[31:0]

RD[31:0]