ICS83940DYI REVISION C May 19, 2016

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©2016 Integrated Device Technology, Inc.

ICS83940DI Data Sheet

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER

LVPECL Clock Input Interface

The PCLK /nPCLK accepts LVPECL, CML, SSTL and other

for the PCLK/nPCLK input driven by the most common driver types.

The input interfaces suggested here are examples only. If the driver

is from another vendor, use their termination recommendation.

Please consult with the vendor of the driver component to confirm the

driver termination requirements.

Figure 2A. PCLK/nPCLK Input Driven by a CML Driver

Figure 2C. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver

Figure 2E. PCLK/nPCLK Input Driven by an SSTL Driver

Figure 2B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 2D. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver with AC Couple

PCLK

nPCLK

LVPECL

Input

CML

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

3.3V

R1

50

Ω

R2

50

Ω

R3

125

Ω

R4

125

Ω

R1

84

Ω

R2

84

Ω

3.3V

Zo = 50

Ω

Zo = 50

Ω

PCLK

nPCLK

3.3V

3.3V

LVPECL

LVPECL

Input

PCLK

nPCLK

LVPECL

Input

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

R1

120

R2

120

R3

120

R4

120

PCLK

nPCLK

3.3V

LVPECL

Input

3.3V

Zo = 50

Ω

Zo = 50

Ω

R1

100

Ω

CML Built-In Pullup