SRAM

AS5LC512K8

AS5LC512K8

Rev. 2.4 10/13

Micross Components reserves the right to change products or specifications without notice.

2

FUNCTIONAL BLOCK DIAGRAM

TRUTH TABLE

MODE

OE\ CE\ WE\

I/O

POWER

STANDBY

X

H

X

HIGH-Z STANDBY

READ

L

L

H

Q

ACTIVE

NOT SELECTED

H

L

H

HIGH-Z ACTIVE

WRITE

X

L

L

D

ACTIVE

S

N

O

I

T

C

N

U

F

N

I

P

8

1

A

-

0

As

t

u

p

n

I

s

s

e

r

d

d

A

\

E

We

l

b

a

n

E

e

t

i

r

W

\

E

Ce

l

b

a

n

E

p

i

h

C

\

E

Oe

l

b

a

n

E

t

u

p

t

u

O

O

/

I

0

O

/

I

-

7

s

t

u

p

t

u

O

/

s

t

u

p

n

I

a

t

a

D

V

C

C

r

e

w

o

P

V

S

S

d

n

u

o

r

G

C

Nn

o

i

t

c

e

n

n

o

C

o

N

X = Don’t Care

VCC

GND

4,194,304-BIT

MEMORY ARRAY

1024 ROWS X

4096 COLUMNS

COLUMN DECODER

*POWER

DOWN

CE\

OE\

WE\

DQ8

DQ1

A0-A18

*On the low voltage Data Retention option.

GENERAL DESCRIPTION

The AS5LC512K8 is a 3.3V high speed SRAM. It offers flex-

ibility in high-speed memory applications, with chip enable (CE\) and

output enable (OE\) capabilities. These features can place the outputs

in High-Z for additional flexibility in system design.

Writing to these devices is accomplished when write enable (WE\)

and CE\ inputs are both LOW. Reading is accomplished when WE\

remains HIGH and CE\ and OE\ go LOW.

As a option, the device can be supplied offering a reduced power

standby mode, allowing system designers to meet low standby power

requirements. This device operates from a single +3.3V power supply

and all inputs and outputs are fully TTL-compatible.

The AS5LC512K8DJ offers the convenience and reliability of

the AS5LC512K8 SRAM and has the cost advantage of a plastic en-

capsulation. TSOPII with copper lead frames offers superior thermal

performance.