BLUENRG-1 datasheet(6/173 Pages) STMICROELECTRONICS

6 / 173 page

List of tables

BlueNRG-1

6/173

DocID028866 Rev 1

Table 41: DMA_CHx - CCR register description: address offset DMA_CHX_BASE_ADDR+0x00.........48

Table 42: DMA_CHx - CNDTR register description: address offset DMA_CHX_BASE_ADDR+0x04 ....49

Table 43: DMA_CHx - CPAR register description: address offset DMA_CHX_BASE_ADDR+0x08.......49

Table 44: DMA_CHx - CMAR register description: address offset DMA_CHX_BASE_ADDR+0x0C .....49

Table 45: SPI clock phase and clock polarity ...........................................................................................50

Table 46: SPI TX endianness ...................................................................................................................51

Table 47: SPI RX endianness...................................................................................................................51

Table 48: SPI registers .............................................................................................................................54

Table 49: SPI - CR0 register description: address offset SPI_BASE_ADDR+0x00.................................54

Table 50: SPI - CR1 register description: address offset SPI_BASE_ADDR+0x04.................................55

Table 51: SPI - DR register description: address offset SPI_BASE_ADDR+0x08...................................57

Table 52: SPI - SR register description: address offset SPI_BASE_ADDR+0x0C ..................................57

Table 53: SPI - CPSR register description: address offset SPI_BASE_ADDR+0x10..............................57

Table 54: SPI - IMSC register description. Address offset SPI_BASE_ADDR+0x14. .............................58

Table 55: SPI - RIS register description: address offset SPI_BASE_ADDR+0x18 ..................................58

Table 56: SPI - MIS register description: address offset SPI_BASE_ADDR+0x1C .................................58

Table 57: SPI - ICR register description: address offset SPI_BASE_ADDR+0x20..................................59

Table 58: SPI - DMACR register description: address offset SPI_BASE_ADDR+0x24...........................59

Table 59: SPI

– RXFRM register description: address offset SPI_BASE_ADDR+0x28 ..........................59

Table 60: SPI

– CHN register description: address offset SPI_BASE_ADDR+0x2C...............................59

Table 61: SPI

– WDTXF register description: address offset SPI_BASE_ADDR + 0x30 ........................60

Table 62: SPI - ITCR register description: address offset SPI_BASE_ADDR+0x80 ...............................60

Table 63: SPI

– TDR register description: address offset SPI_BASE_ADDR+0x8C ...............................60

Table 64: RX FIFO errors .........................................................................................................................61

Table 65: Typical baud rates with OVSFACT = 0.....................................................................................63

Table 66: Typical baud rates with OVSFACT = 1.....................................................................................64

Table 67: Control bits to enable and disable hardware flow control .........................................................65

Table 68: Control bits to enable and program receive software flow control............................................65

Table 69: Control bits to enable and program transmit software flow control ..........................................66

Table 70: UART registers .........................................................................................................................69

Table 71: UART - DR register description: address offset UART_BASE_ADDR+0x00...........................70

Table 72: UART - RSR register description: address offset UART_BASE_ADDR+0x04 ........................70

Table 73: UART - TIMEOUT register description: address offset UART_BASE_ADDR+0x0C ...............71

Table 74: UART - FR register description: address offset UART_BASE_ADDR+0x18 ...........................71

Table 75: UART - LCRH_RX register description: address offset UART_BASE_ADDR+0x1C ..............72

Table 76: UART - IBRD register description: address offset UART_BASE_ADDR+0x24 .......................73

Table 77: UART - FBRD register description: address offset UART_BASE_ADDR+0x28 ......................73

Table 78: UART - LCRH_TX register description: address offset UART_BASE_ADDR+0x2C...............74

Table 79: UART - CR register description: address offset UART_BASE_ADDR+0x30...........................75

Table 80: UART - IFLS register description: address offset UART_BASE_ADDR+0x34 ........................76

Table 81: UART - IMSC register description: address offset UART_BASE_ADDR+0x38 .......................76

Table 82: UART - RIS register description: address offset UART_BASE_ADDR+0x3C .........................77

Table 83: UART - MIS register description: address offset UART_BASE_ADDR+0x40 .........................78

Table 84: UART - ICR register description: address offset UART_BASE_ADDR+0x44..........................79

Table 85: UART - DMACR register description: address offset UART_BASE_ADDR+0x48 ..................80

Table 86: UART - XFCR register description: address offset UART_BASE_ADDR+0x50 ......................80

Table 87: UART - XON1 register description: address offset UART_BASE_ADDR+0x54 ......................81

Table 88: UART - XON2 register description. Address offset UART_BASE_ADDR+0x58. ....................81

Table 89: UART - XOFF1 register description. Address offset UART_BASE_ADDR+0x5C. ..................81

Table 90: UART - XOFF2 register description. Address offset UART_BASE_ADDR+0x60....................81

Table 91: I2Cx registers............................................................................................................................84

Table 92: I2C - CR register description: address offset I2CX_BASE_ADDR+0x00.................................85

Table 93: I2C - SCR register description: address offset I2CX_BASE_ADDR+0x04 ..............................87

Table 94: I2C2 - MCR register description: address offset I2CX_BASE_ADDR+0x0C ...........................87

Table 95: I2C - TFR register description: address offset I2CX_BASE_ADDR+0x10...............................89

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