LAN9215 datasheet(45/144 Pages) SMSC

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16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9215

Revision 2.9 (03-01-12)

DATASHEET

3.10.1

Power-On Reset (POR)

A Power-On reset occurs whenever power is initially applied to the LAN9215, or if power is removed

and reapplied to the LAN9215. A timer within the LAN9215 will assert the internal reset for

approximately 22ms. The READY bit in the PMT_CTRL register can be read from the host interface

and will read back a ‘0’ until the POR is complete. Upon completion of the POR, the READY bit in

PMT_CTRL is set high, and the LAN9215 can be configured via its control registers.

APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal

reset (22ms). If the software driver polls this bit and it is not set within 100ms, then an error

condition occurred.

3.10.2

Hardware Reset Input (nRESET)

A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the

PMT_CTRL register can be read from the host interface, and will read back a ‘0’ until the hardware

reset is complete. Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high.

After the “READY” bit is set, the LAN9215 can be configured via its control registers. The nRESET

signal is pulled-high internally by the LAN9215 and can be left unconnected if unused. If used,

nRESET must be driven low for a minimum period as defined in Section 6.8, "Reset Timing," on

page 131.

APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately. If

the software driver polls this bit and it is not set within 100ms, then an error condition

occurred.

3.10.3

Resume Reset Timing

After issuing a write to the BYTE_TEST register to wake the LAN9215 from a power-down state, the

READY bit in PMT_CTRL will assert (set High) within 2ms.

APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If

the software driver polls this bit and it is not set within 100ms, then an error condition

occurred.

3.10.4

Soft Reset (SRST)

Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will

return to ‘0’ after approximately 2

μs, at which time the Soft Reset is complete. Soft reset does not

clear control register bits marked as NASR.

APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately,

(within 2

μs). If the software driver polls this bit and it is not set within 100ms, then an error

condition occurred.

3.10.5

PHY Reset Timing

The following sections specify the operation and time required for the internal PHY to become

operational after various resets or when returning from the reduced power state.

3.10.5.1

PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)

The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This

self-clearing bit will return to ‘0’ after approximately 100

μs, at which time the PHY reset is complete.

LAN9215 Datasheet(PDF) 45 Page - SMSC Corporation

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