LAN9215-MT datasheet(85/144 Pages) SMSC

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16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9215

Revision 2.9 (03-01-12)

DATASHEET

External PHY Detect (EXT_PHY_DET). This bit reflects the latched value

of the EXT_PHY_DET strap. The EXT_PHY_DET strap is used to indicate

the presence of an external PHY. This strap is latched from the value of the

external MDIO signal upon power-up or hard reset. If MDIO is pulled high a

‘1’ will be seen in this bit. If MDIO is pulled low a ‘0’ will be seen in this bit.

The EXT_PHY_DET strap has no other effect on the internal logic. Its only

function is to give the system designer a mechanism to indicate the

presence of an external PHY to a software application.

Dependant

EXT_PHY_D

ET strap pin

External PHY Enable (EXT_PHY_EN). When set to a ‘1’, this bit enables

the external MII port. When cleared, the internal PHY is enabled and the

external MII port is disabled.

Notes:

This signal does not control multiplexing of the SMI port or the TX_CLK

or RX_CLK signals.

There are restrictions on the use of this bit. Please refer to Section 3.11,

"MII Interface - External MII Switching," on page 46 for details.

Soft Reset Timeout (SRST_TO). If a software reset is attempted when the

internal PHY is not in the operational state (RX_CLK and TX_CLK running), the reset

will not complete and the soft reset operation will timeout and this bit will be set to a

‘1’. The host processor must correct the problem and issue another soft reset.

Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset

generates a full reset of the MAC CSR’s. The SCSR’s (system command

and status registers) are reset except for any NASR bits. Soft reset also

clears any TX or RX errors (TXE/RXE). This bit is self-clearing.

Notes:

Do not attempt a soft reset unless the internal PHY is fully awake and

operational. After a PHY reset, or when returning from a reduced power

state, the PHY must given adequate time to return to the operational state

before a soft reset can be issued. The internal RX_CLK and TX_CLK

signals must be running for a proper software reset. Please refer to

Section 6.8, "Reset Timing," on page 131 for details on PHY reset timing.

The LAN9215 must always be read at least once after power-up, reset, or

upon return from a power-saving state or write operations will not function.

BITS

DESCRIPTION

TYPE

DEFAULT

LAN9215-MT Datasheet(PDF) 85 Page - SMSC Corporation

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