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LAN91C100FD Datasheet(PDF) 39 Page - SMSC Corporation

Part # LAN91C100FD
Description  FEAST Fast Ethernet Controller with Full Duplex Capability
PDF  77 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN91C100FD Datasheet(HTML) 39 Page - SMSC Corporation

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FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC LAN91C100FD Rev. D
Page 39
Revision 1.0 (09-22-08)
DATASHEET
FLTST - Facilitates the inclusion of packet forwarding information on the receive packet memory structure.
When 0, RD0-RD7 is always driven. When 1, RD0-RD7 is floated during RECEIVE FRAME STATUS
WORD writes (RA2-RA16=0, RCVDMA=1, nRWE0-nRWE3=0).
MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0).
MDO - MII Management output. The value of this bit drives the MDO pin.
MDI - MII Management input. The value of the MDI pin is readable using this bit.
MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.
MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-stated.
The purpose of this interface, along with the corresponding pins is to implement MII PHY management in
software.
BANK 3
OFFSET
NAME
TYPE
SYMBOL
A
REVISION REGISTER
READ ONLY
REV
HIGH
BYTE
0
0
1
1
0
0
1
1
LOW
BYTE
CHIP
REV
1
0
0
0
0
0
0
0
CHIP - Chip ID. Can be used by software drivers to identify the device used.
REV - Revision ID. Incremented for each revision of a given device.
OFFSET
NAME
TYPE
SYMBOL
C
RCV REGISTER
READ/WRITE
RCV
HIGH
BYTE
nRXDISC PIN COUNTER
0
0
0
0
0
0
0
0
LOW
BYTE
RCV
DISCR
D
0
0
MBO
MBO
MBO
MBO
MBO
0
0
0
1
1
1
1
1
nRXDISC PIN COUNTER - 8-bit counter increments when a packet is discarded due to the nRXDISC pin
being active. This counter will be reset to 00 when read. A count of FF will set the RX_DISC INT. The
count will wrap around to 00 after FF.
RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being
received. When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will
be set to indicate that the packet was discarded. Otherwise, the packet will be received normally and bit 0
set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing.
MBO – Must be 1.



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