AD6315 datasheet(2/16 Pages) ANACHIP

2 / 16 page

AD6315

1/4- to 1/12 Duty VFD Controller/Driver

Anachip Corp.

www.anachip.com.tw

Rev. A5 Dec 29, 2003

2/16

Pin Descriptions

Symbol

Name

No.

Description

DIN

Data input

Input serial data at rising edge of shift clock,

starting from the low order bit.

DOUT

Data output

Output serial data at the falling edge of the

shift clock, starting from low order bit. This is

N-ch open-drain output pin.

STB

Strobe

Initializes serial interface at the rising or

falling edge of the AD6315. It then waits for

reception of a command. Data input after

STB falling is processed as a command.

While command data is processed, current

processing is stopped, and the serial

interface is initialized. While STB is high, CLK

is ignored.

CLK

Clock input

Reads serial data at the rising edge, and

outputs data at the falling edge.

OSC

Oscillator pin

Connect resistor in between this pin and Vss to set

up the oscillation frequency.

Seg1/KS1 to

Seg16/KS16

High-voltage output (Segment)

14 to 29

Segment output pins (Dual function as key

source)

Grid1 to Grid4

High-voltage output (Grid)

39 to 42 Grid output pins

Seg17/Grid12 to

Seg24/Grid5

High-voltage output

(Segment/grid)

31 to 38

These pins are selectable for segment or grid

driving.

LED1 to LED4

LED output

1 to 4

CMOS output

KEY1, KEY2

Key data input

10, 11

Data input to these pins is latched at the end

of the display cycle.

VDD

Logic power

13, 43

Logic power supply

VSS

Logic ground

12, 44

Connect this pin to system GND.

VEE

Pull-down level

Driver power supply

Ordering Information

AD6315X X X

Packing

Blank : Tray

Q: QFP-44L

L : LQFP-44L

Package

Lead

Blank: Normal

F: Lead Free

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